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| touch key flash type 8-bit mcu with lcd/led driver bs85b12-3/BS85C20-3 revision: v1.00 date: february 1, 2011
table of contents technical document ...........................................................................1 features ...............................................................................................1 cpu features ........................................................................................................1 peripheral features ................................................................................................1 general description ............................................................................2 selection table ....................................................................................2 block diagram .....................................................................................2 pin assignment ...................................................................................3 pin description ....................................................................................4 bs85b12-3 .............................................................................................................4 BS85C20-3 .............................................................................................................7 absolute maximum ratings .............................................................11 d.c. characteristics ..........................................................................11 a.c. characteristics ..........................................................................13 power-on reset characteristics ......................................................14 oscillator temperature/frequency characteristics .......................14 system architecture .........................................................................17 clocking and pipelining ........................................................................................17 program counter ..................................................................................................18 stack ....................................................................................................................18 arithmetic and logic unit alu ...........................................................................19 flash program memory ....................................................................21 structure ...............................................................................................................21 special vectors .....................................................................................................22 look-up table .......................................................................................................22 table program example .....................................................................................22 in circuit programming .........................................................................................23 ram data memory.............................................................................22 structure ...............................................................................................................22 contents i special function register description ...........................................23 indirect addressing registers iar0, iar1 ..........................................................23 memory pointers mp0, mp1 ..............................................................................23 bank pointer bp ................................................................................................25 accumulator acc ..............................................................................................26 program counter low register pcl..................................................................26 look-up table registers tblp, tbhp, tblh .....................................................26 status register status ...................................................................................26 eeprom data memory .....................................................................28 eeprom data memory structure ........................................................................28 reading data from the eeprom .........................................................................30 writing data to the eeprom ...............................................................................30 write protection ....................................................................................................30 eeprom interrupt ...............................................................................................30 programming considerations ...............................................................................31 programming examples .......................................................................................31 oscillator............................................................................................32 oscillator overview ...............................................................................................32 system clock configurations ................................................................................32 internal high speed rc oscillator hirc ............................................................32 internal low speed rc oscillator lirc .............................................................33 operating modes and system clocks .............................................34 system clocks ......................................................................................................34 control register ...................................................................................................35 system operation modes .....................................................................................36 operating mode switching ....................................................................................37 normal mode to slow mode switching ...........................................................38 slow mode to normal mode switching ...........................................................38 entering the sleep mode ....................................................................................38 entering the idle0 mode .....................................................................................39 entering the idle1 mode .....................................................................................39 standby current considerations ...........................................................................39 wake-up ...............................................................................................................40 programming considerations ...............................................................................40 watchdog timer ................................................................................41 watchdog timer clock source .............................................................................41 watchdog timer control register .........................................................................41 watchdog timer operation ...................................................................................42 reset and initialisation .....................................................................43 reset functions ...................................................................................................43 reset initial conditions .........................................................................................44 ii contents input/output ports.............................................................................49 i/o register list ....................................................................................................49 pull-high resistors ................................................................................................50 port a wake-up ....................................................................................................51 i/o port control register ......................................................................................51 pin re-mapping functions ...................................................................................52 i/o pin structures .................................................................................................56 programming considerations ...............................................................................56 timer modules tm..........................................................................57 introduction ..........................................................................................................57 tm operation .......................................................................................................57 tm clock source ..................................................................................................58 tm interrupts ........................................................................................................58 tm external pins ..................................................................................................58 tm input/output pin control registers .................................................................60 programming considerations ...............................................................................62 compact type tm ctm..................................................................63 compact tm operation ........................................................................................63 compact type tm register description ...............................................................64 compact type tm operating modes ....................................................................67 compare match output mode ..............................................................................67 timer/counter mode .............................................................................................69 pwm output mode ...............................................................................................70 standard type tm stm..................................................................72 standard tm operation ........................................................................................72 standard type tm register description ...............................................................73 standard type tm operating modes ....................................................................77 enhanced type tm etm ................................................................84 enhanced tm operation ......................................................................................84 enhanced type tm register description ..............................................................85 enhanced type tm operating modes ..................................................................90 compare output mode .........................................................................................91 timer/counter mode .............................................................................................95 pwm output mode ...............................................................................................95 single pulse output mode ..................................................................................101 capture input mode ............................................................................................103 touch key function ........................................................................105 touch key structure ...........................................................................................105 touch key register definition .............................................................................105 touch key operation ..........................................................................................110 touch key interrupt .............................................................................................110 programming considerations .............................................................................110 contents iii serial interface module sim .........................................................111 spi interface .......................................................................................................111 i 2 c interface ........................................................................................................117 peripheral clock output .................................................................126 peripheral clock operation .................................................................................126 interrupts..........................................................................................127 interrupt registers ..............................................................................................127 interrupt register contents .................................................................................128 interrupt operation .............................................................................................134 external interrupt ................................................................................................136 multi-function interrupt ........................................................................................136 time base interrupts ..........................................................................................136 external peripheral interrupt ...............................................................................138 lvd interrupt ......................................................................................................138 tm interrupts ......................................................................................................138 eeprom interrupt .............................................................................................139 touch key interrupts ...........................................................................................139 sim interrupt .......................................................................................................139 interrupt wake-up function ................................................................................139 programming considerations .............................................................................140 low voltage detector lvd ...........................................................140 lvd register ......................................................................................................140 lvd operation ....................................................................................................141 lcd driver scom and sseg function ......................................142 lcd operation ...................................................................................................142 lcd bias control ................................................................................................144 lcd driver registers ..........................................................................................144 led driver........................................................................................146 led driver operation .........................................................................................146 led driver registers ..........................................................................................146 application circuits ........................................................................148 instruction set .................................................................................149 introduction .........................................................................................................149 instruction timing ...............................................................................................149 moving and transferring data ............................................................................149 arithmetic operations .........................................................................................149 logical and rotate operations ...........................................................................149 branches and control transfer ...........................................................................149 bit operations .....................................................................................................149 iv contents table read operations .......................................................................................149 other operations ................................................................................................150 instruction set summary ....................................................................................151 instruction definition ......................................................................153 package information .......................................................................163 24-pin skdip (300mil) outline dimensions ........................................................163 24-pin sop (300mil) outline dimensions ............................................................166 24-pin ssop (150mil) outline dimensions .........................................................167 28-pin skdip (300mil) outline dimensions ........................................................168 28-pin sop (300mil) outline dimensions ............................................................169 28-pin ssop (150mil) outline dimensions .........................................................170 44-pin qfp (10mm 10mm) outline dimensions ................................................171 reel dimensions ................................................................................................172 carrier tape dimensions ....................................................................................173 contents v technical document application note ha0075e mcu reset and oscillator circuits application note features cpu features operating voltage: f sys = 8mhz: v lvr ~5.5v f sys = 12mhz: 2.7v~5.5v f sys = 16mhz: 4.5v~5.5v power down and wake-up functions to reduce power consumption fully integrated low and high speed internal oscillators low speed -- 32khz high speed -- 8mhz, 12mhz, 16mhz multi-mode operation: normal, slow, idle and sleep all instructions executed in one or two instruction cycles table read instructions 63 powerful instructions up to 4 subroutine nesting levels bit manipulation instruction peripheral features fully integrated 12 or 20 touch key functions -- require no external components flash program memory: 2k 15 or 4k 15 ram data memory: 256 8 or 384 8 eeprom memory: 64 8 or 128 8 watchdog timer function up to 38 bidirectional i/o lines two or three timer modules dual time-base functions for generation of fixed time interrupt signals i 2 c and spi interfaces low voltage reset function software controlled 4 14 or 4 22 lcd driver with 1/3 bias software controlled 6 8or8 14 led driver bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 1 february 1, 2011 general description these devices are a series of flash memory type 8-bit high performance risc architecture microcontrollers with fully integrated touch key functions and lcd/led drivers. with all touch key functions provided internally and with the convenience of flash memory multi-programming features, this device range has all the features to offer designers a reliable and easy means of implementing touch keys within their products applications. the touch key functions are fully integrated completely eliminating the need for external components. the inclusion of both lcd and led driver functions allows for easy and cost effective solutions in applications that require to interface to these display types. in addition to the flash program memory, other memory includes an area of ram data memory as well as an area of eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. protective features such as an internal watchdog timer, low voltage reset and low voltage detector functions coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. all devices include fully integrated low and high speed oscillators which require no external components for their implementation. the ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. easy communication with the outside world is provided using the internal i 2 c and spi interfaces, while the inclusion of flexible i/o programming features, timer modules and many other features further enhance device functionality and flexibility. these touch key devices will find excellent use in a huge range of modern touch key product applications such as instrumentation, household appliances, electronically controlled tools to name but a few. selection table part no. internal clock vdd system clock program memory data memory data eeprom i/o timer module touch key lcd driver led driver spi/ i 2 c stack package bs85b12-3 8mhz 12mhz 16mhz v lvr ~ 5.5v 8mhz~ 16mhz 2k 15 256 864 8 22 2 12 4 14 6 81 4 24/28skdip/sop 24/28ssop BS85C20-3 8mhz 12mhz 16mhz v lvr ~ 5.5v 8mhz~ 16mhz 4k 15 384 8 128 8 38 3 20 4 22 8 14 1 8 28skdip/sop 28ssop, 44qfp block diagram rev. 1.00 2 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver ! " # $ % & ' " # $ ' ( $ ' ) & * & " # $ % + , - , . pin assignment note: 1. bracketed pin names indicate non-default pinout remapping locations. 2. if the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the / sign can be used for higher priority. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 3 february 1, 2011 / 0 / 1 / / / . / - . 2 . . 3 . 4 . 5 . 0 . 1 . / 1 0 5 4 3 2 . - . . . / - 6 - 7 - 8 6 & 8 9 - + : . . 6 - 7 . 8 6 + " 8 9 . + : / / 6 . , 7 - 8 6 & & * 8 9 / + : 1 1 6 . , 7 . 8 6 8 9 1 + : 0 0 6 + - 8 6 ; - 8 6 . , 7 / 8 9 0 + : 5 5 6 + . 8 6 ; . 8 6 . * 8 9 5 + : 4 4 6 + 8 9 4 + : 3 3 ; 9 3 + : + : . . + : . / % % & & , - - 7 - - , . - 7 . . , / . , 7 - / , 1 . , 7 . 1 * . + . ; . 9 . - * 0 + - ; - 9 . . * 5 9 . / * 4 9 . 1 * 1 * - & & * * / + " * 3 & / / 3 / 4 / 5 / 0 / 1 / / / . / - . 2 . . 3 . 4 . 5 . / 1 0 5 4 3 2 . - . . . / . 1 . 0 - 6 - 7 - 8 6 & 8 9 - + : . . 6 - 7 . 8 6 + 8 6 " 8 9 . + : / / 6 . , 7 - 8 6 & 8 6 & * 8 9 / + : 1 1 6 . , 7 . 8 6 8 9 1 + : 0 0 6 + - 8 6 ; - 8 6 . , 7 / 8 9 0 + : 5 5 6 + . 8 6 ; . 8 6 . * 8 9 5 + : 4 4 + / 6 + 8 9 4 + : 3 3 6 ; 8 9 3 + : + : 2 + : . - + : . . + : . / % % & & , - - 7 - - , . - 7 . / 7 - . , / . , 7 - / 7 . / , 1 . , 7 . 1 , 0 . , 7 / + 9 , 5 ; . * 9 2 * . + . ; . 9 . - * 0 + - ; - 9 . . * 5 9 . / * 4 9 . 1 * 1 * - & & * * / + " * 3 & / / 3 / 4 / 5 / 0 / 1 / / / . / - . 2 . . 3 . 4 . 5 . / 1 0 5 4 3 2 . - . . . / . 1 . 0 - 6 - 7 - 8 6 & 8 9 - + : . . 6 - 7 . 8 6 + 8 6 " 8 9 . + : / / 6 . , 7 - 8 6 & 8 6 & * 8 9 / + : 1 1 6 . , 7 . 8 6 8 9 1 + : 0 0 6 + - 8 6 ; - 8 6 . , 7 / 8 9 0 + : 5 5 6 + . 8 6 ; . 8 6 . * 8 9 5 + : 4 4 6 + 8 9 4 + : 3 3 6 ; 8 9 3 + : + : 2 + : . - + : . . + : . / % % & & , - - 7 - - , . - 7 . . , / . , 7 - / , 1 . , 7 . 1 , 0 . , 7 / + 9 , 5 ; . * 9 2 * . + . ; . 9 . - * 0 + - ; - 9 . . * 5 9 . / * 4 9 . 1 * 1 * - & & * * / + " * 3 & 0 6 + - 8 6 ; - 8 6 . , 7 / 8 9 0 + : 5 5 6 + . 8 6 ; . 8 6 . * 8 9 5 + : 4 4 + / 6 + 8 9 4 + : 3 3 6 ; 8 9 3 + : & - 6 + / 8 + : . 1 & . + : . 0 & / + : . 5 & 1 + : . 4 & 0 + : . 3 & 5 + : . & 4 + : . 2 . / 1 0 5 4 3 2 . - . . . / . 1 . 0 . 5 . 4 . 3 . . 2 / - / . / / / 1 / 0 / 5 / 4 / 3 / / 2 1 - 1 . 1 / 1 1 1 01 51 41 31 1 20 -0 .0 /0 10 0 , 1 . , 7 . 1 , 0 . , 7 / + 9 , 5 ; . * 9 2 , 4 9 / - , 3 9 / . 0 6 & 8 6 & * 8 9 . 5 6 & 8 9 . 2 * . + . ; . 9 . - * 0 + - ; - 9 . . * 5 9 . / * 4 9 . 1 * 1 * - & & * * / + " * 3 & % & & % + : . / + : . . + : . - + : 2 & 3 + : / - , / . , 7 - / 7 . / , . - 7 . / 7 - . , - - 7 - - 1 6 + 8 6 " 8 9 . 3 / 6 / 7 . 8 6 8 9 . 4 . 6 / 7 - 8 6 + 8 9 . 5 - 6 ; 8 9 . 0 - 6 - 7 - 8 6 & 8 9 - + : . . 6 - 7 . 8 6 + 8 6 " 8 9 . + : / / 6 . , 7 - 8 6 & 8 6 & * 8 9 / + : 1 1 6 . , 7 . 8 6 8 9 1 + : 0 pin description the function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. bs85b12-3 pin name function register select i/t o/t description pa0/sdi/sda pa0 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. sdi simc0 st spi data input sda simc0 st nmos i 2 c data i/o pa1/tck1/ int1/sseg10 pa1 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. tck1 tm1c0 st timer module 1 input int1 intc0 st external interrupt 1 input sseg10 slcdcn lcd software controlled lcd seg pa2/sck/scl pa2 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. sck simc0 st cmos spi serial clock scl simc0 st nmos i 2 c clock pa3/scs pa3 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. scs simc0 st cmos spi slave select pa4/tck0/ int0/sseg11 pa4 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. tck0 tm0c0 st timer module 0 input int0 intc0 st external interrupt 0 input sseg11 slcdcn lcd software controlled lcd seg pa5/sseg12 pa5 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. sseg12 slcdcn lcd software controlled lcd seg pa6/sseg13 pa6 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. sseg13 slcdcn lcd software controlled lcd seg pa7/sdo pa7 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. sdo simc0 cmos spi data output pb0/tp0_0/ scom0 pb0 pbpu st cmos general purpose i/o. register enabled pull-up. tp0_0 tmpcn st cmos tm0 i/o scom0 slcdcn lcd software controlled lcd com pb1/tp0_1/ scom1 pb1 pbpu st cmos general purpose i/o. register enabled pull-up. tp0_1 tmpcn st cmos tm0 i/o scom1 slcdcn lcd software controlled lcd com rev. 1.00 4 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver pin name function register select i/t o/t description pb2/tp1b_0/ scom2 pb2 pbpu st cmos general purpose i/o. register enabled pull-up. tp1b_0 tmpcn st cmos tm1 i/o scom2 slcdcn lcd software controlled lcd com pb3/tp1b_1/ scom3 pb3 pbpu st cmos general purpose i/o. register enabled pull-up. tp1b_1 tmpcn st cmos tm1 i/o scom3 slcdcn lcd software controlled lcd com pb4/tp1b_2/ pck/sseg8 pb4 pbpu st cmos general purpose i/o. register enabled pull-up. tp1b_2 tmpcn st cmos tm1 i/o pck simc0 cmos peripheral clock output sseg8 slcdcn lcd software controlled lcd seg pb5/pint / tp1a/sseg9 pb5 pbpu st cmos general purpose i/o. register enabled pull-up. pint mfi3 st peripheral interrupt input tp1a tmpcn st cmos tm1 i/o sseg9 slcdcn lcd software controlled lcd seg pc0/tp0_0/ sdo/sseg0/ key1 pc0 pcpu st cmos general purpose i/o. register enabled pull-up. tp0_0 tmpcn st cmos tm0 i/o sdo simc0 cmos spi data output sseg0 slcdcn lcd software controlled lcd seg key1 tkmnc1 ns touch key input pc1/tp0_1/ sck/scl/ sseg1/key2 pc1 pcpu st cmos general purpose i/o. register enabled pull-up. tp0_1 tmpcn st cmos tm0 i/o sck simc0 st cmos spi clock scl simc0 st nmos i 2 c clock sseg1 slcdcn lcd software controlled lcd seg key2 tkmnc1 ns touch key input pc2/tp1b_0/ sdi/sda/ sseg2/key3 pc2 pcpu st cmos general purpose i/o. register enabled pull-up. tp1b_0 tmpcn st cmos tm1 i/o sdi simc0 st spi data input sda simc0 st nmos i 2 c data i/o sseg2 slcdcn lcd software controlled lcd seg key3 tkmnc1 ns touch key input pc3/tp1b_1/ scs /sseg3/ key4 pc3 pcpu st cmos general purpose i/o. register enabled pull-up. tp1b_1 tmpcn st cmos tm1 i/o scs simc0 st cmos spi slave select sseg3 slcdcn lcd software controlled lcd seg key4 tkmnc1 ns touch key input bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 5 february 1, 2011 pin name function register select i/t o/t description pc4/tck0/ int0/tp1b_2/ sseg4/key5 pc4 pcpu st cmos general purpose i/o. register enabled pull-up. tck0 tm0c0 st timer module 0 input int0 intc0 st external interrupt 0 input tp1b_2 tmpcn st cmos tm1 i/o sseg4 slcdcn lcd software controlled lcd seg key5 tkmnc1 ns touch key input pc5/tck1/ int1/tp1a/ sseg5/key6 pc5 pcpu st cmos general purpose i/o. register enabled pull-up. tck1 tm1c0 st timer module 1 input int1 intc0 st external interrupt 1 input tp1a tmpcn st cmos tm1 i/o sseg5 slcdcn lcd software controlled lcd seg key6 tkmnc1 ns touch key input pc6/pck/ sseg6/key7 pc6 pcpu st cmos general purpose i/o. register enabled pull-up. pck simc0 cmos peripheral clock output sseg6 slcdcn lcd software controlled lcd seg key7 tkmnc1 ns touch key input pc7/pint / sseg7/key8 pc7 pcpu st cmos general purpose i/o. register enabled pull-up. pint mfi3 st peripheral interrupt input sseg7 slcdcn lcd software controlled lcd seg key8 tkmnc1 ns touch key input key9 key9 ns touch key input key10 key10 ns touch key input key11 key11 ns touch key input key12 key12 ns touch key input vdd vdd pwr power supply vss vss pwr ground note: i/t: input type o/t: output type register select: indicates register which selects alternative function pwr: power st: schmitt trigger input cmos: cmos output nmos: nmos output lcd: lcd com or seg vbias output ns: non-standard input or output the pins in the table reflect that of the package with the largest number of pins. for this reason not all pins may exist on all package types. rev. 1.00 6 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver BS85C20-3 pin name function register select i/t o/t description pa0/sdi/sda pa0 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. sdi simc0 st spi data input sda simc0 st nmos i 2 c data i/o pa1/tck1/ int1/sseg10 pa1 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. tck1 tm1c0 st timer module 1 input int1 intc0 st external interrupt 1 input sseg10 slcdcn lcd software controlled lcd seg pa2/sck/scl pa2 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. sck simc0 st cmos spi serial clock scl simc0 st nmos i 2 c clock pa3/scs pa3 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. scs simc0 st cmos spi slave select pa4/tck0/ int0/sseg11 pa4 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. tck0 tm0c0 st timer module 0 input int0 intc0 st external interrupt 0 input sseg11 slcdcn lcd software controlled lcd seg pa5/sseg12 pa5 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. sseg12 slcdcn lcd software controlled lcd seg pa6/sseg13 pa6 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. sseg13 slcdcn lcd software controlled lcd seg pa7/sdo pa7 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. sdo simc0 cmos spi data output pb0/tp0_0/ scom0 pb0 pbpu st cmos general purpose i/o. register enabled pull-up. tp0_0 tmpcn st cmos tm0 i/o scom0 slcdcn lcd software controlled lcd com pb1/tp0_1/ tp2_0/scom1 pb1 pbpu st cmos general purpose i/o. register enabled pull-up. tp0_1 tmpcn st cmos tm0 i/o tp2_0 tmpcn st cmos tm2 i/o scom1 slcdcn lcd software controlled lcd com pb2/tp1b_0/ tp2_1/ scom2 pb2 pbpu st cmos general purpose i/o. register enabled pull-up. tp1b_0 tmpcn st cmos tm1 i/o tp2_1 tmpcn st cmos tm2 i/o scom2 slcdcn lcd software controlled lcd com bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 7 february 1, 2011 pin name function register select i/t o/t description pb3/tp1b_1/ scom3 pb3 pbpu st cmos general purpose i/o. register enabled pull-up. tp1b_1 tmpcn st cmos tm1 i/o scom3 slcdcn lcd software controlled lcd com pb4/tp1b_2/ pck/sseg8 pb4 pbpu st cmos general purpose i/o. register enabled pull-up. tp1b_2 tmpcn st cmos tm1 i/o pck simc0 cmos peripheral clock output sseg8 slcdcn lcd software controlled lcd seg pb5/pint / tp1a/sseg9 pb5 pbpu st cmos general purpose i/o. register enabled pull-up. pint mfi3 st peripheral interrupt input tp1a tmpcn st cmos tm1 i/o sseg9 slcdcn lcd software controlled lcd seg pb6/sseg20 pb6 pbpu st cmos general purpose i/o. register enabled pull-up. sseg20 slcdcn lcd software controlled lcd seg pb7/sseg21 pb7 pbpu st cmos general purpose i/o. register enabled pull-up. sseg21 slcdcn lcd software controlled lcd seg pc0/tp0_0/ sdo/sseg0/ key1 pc0 pcpu st cmos general purpose i/o. register enabled pull-up. tp0_0 tmpcn st cmos tm0 i/o sdo simc0 cmos spi data output sseg0 slcdcn lcd software controlled lcd seg key1 tkmnc1 ns touch key input pc1/tp0_1/ sck/scl/ sseg1/key2 pc1 pcpu st cmos general purpose i/o. register enabled pull-up. tp0_1 tmpcn st cmos tm0 i/o sck simc0 st cmos spi clock scl simc0 st nmos i 2 c clock sseg1 slcdcn lcd software controlled lcd seg key2 tkmnc1 ns touch key input pc2/tp1b_0/ sdi/sda/ sseg2/key3 pc2 pcpu st cmos general purpose i/o. register enabled pull-up. tp1b_0 tmpcn st cmos tm1 i/o sdi simc0 st spi data input sda simc0 st nmos i 2 c data i/o sseg2 slcdcn lcd software controlled lcd seg key3 tkmnc1 ns touch key input pc3/tp1b_1/ scs /sseg3/ key4 pc3 pcpu st cmos general purpose i/o. register enabled pull-up. tp1b_1 tmpcn st cmos tm1 i/o scs simc0 st cmos spi slave select sseg3 slcdcn lcd software controlled lcd seg key4 tkmnc1 ns touch key input rev. 1.00 8 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver pin name function register select i/t o/t description pc4/tck0/ int0/tp1b_2/ sseg4/key5 pc4 pcpu st cmos general purpose i/o. register enabled pull-up. tck0 tm0c0 st timer module 0 input int0 intc0 st external interrupt 0 input tp1b_2 tmpcn st cmos tm1 i/o sseg4 slcdcn lcd software controlled lcd seg key5 tkmnc1 ns touch key input pc5/tck1/ int1/tp1a/ sseg5/key6 pc5 pcpu st cmos general purpose i/o. register enabled pull-up. tck1 tm1c0 st timer module 1 input int1 intc0 st external interrupt 1 input tp1a tmpcn st cmos tm1 i/o sseg5 slcdcn lcd software controlled lcd seg key6 tkmnc1 ns touch key input pc6/tck2/ pck/sseg6/ key7 pc6 pcpu st cmos general purpose i/o. register enabled pull-up. tck2 tm2c0 st timer module 2 input pck simc0 cmos peripheral clock output sseg6 slcdcn lcd software controlled lcd seg key7 tkmnc1 ns touch key input pc7/pint / sseg7/key8 pc7 pcpu st cmos general purpose i/o. register enabled pull-up. pint mfi3 st peripheral interrupt input sseg7 slcdcn lcd software controlled lcd seg key8 tkmnc1 ns touch key input pd0/tck2/ key13 pd0 pdpu st cmos general purpose i/o. register enabled pull-up. tck2 tm2c0 st timer module 2 input key13 tkmnc1 ns touch key input pd1/key14 pd1 pdpu st cmos general purpose i/o. register enabled pull-up. key14 tkmnc1 ns touch key input pd2/key15 pd2 pdpu st cmos general purpose i/o. register enabled pull-up. key15 tkmnc1 ns touch key input pd3/key16 pd3 pdpu st cmos general purpose i/o. register enabled pull-up. key16 tkmnc1 ns touch key input pd4/key17 pd4 pdpu st cmos general purpose i/o. register enabled pull-up. key17 tkmnc1 ns touch key input pd5/key18 pd5 pdpu st cmos general purpose i/o. register enabled pull-up. key18 tkmnc1 ns touch key input pd6/key19 pd6 pdpu st cmos general purpose i/o. register enabled pull-up. key19 tkmnc1 ns touch key input pd7/key20 pd7 pdpu st cmos general purpose i/o. register enabled pull-up. key20 tkmnc1 ns touch key input bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 9 february 1, 2011 pin name function register select i/t o/t description pe0/pint / sseg14 pe0 pepu st cmos general purpose i/o. register enabled pull-up. pint mfi3 st peripheral interrupt input sseg14 slcdcn lcd software controlled lcd seg pe1/tp2_0/ pck/sseg15 pe1 pepu st cmos general purpose i/o. register enabled pull-up. tp2_0 tmpcn st cmos tm2 i/o pck simc0 cmos peripheral clock output sseg15 slcdcn lcd software controlled lcd seg pe2/tp2_1/ scs /sseg16 pe2 pepu st cmos general purpose i/o. register enabled pull-up. tp2_1 tmpcn st cmos tm2 i/o scs simc0 st cmos spi select sseg16 slcdcn lcd software controlled lcd seg pe3/sck/ scl/sseg17 pe3 pepu st cmos general purpose i/o. register enabled pull-up. sck simc0 st cmos spi serial clock scl simc0 st nmos i 2 c clock sseg17 slcdcn lcd software controlled lcd seg pe4/sdi/ sda/sseg18 pe4 pepu st cmos general purpose i/o. register enabled pull-up. sdi simc0 st spi data input sda simc0 st nmos i 2 c data i/o sseg18 slcdcn lcd software controlled lcd seg pe5/sdo/ sseg19 pe5 pepu st cmos general purpose i/o. register enabled pull-up. sdo simc0 st cmos spi data output sseg19 slcdcn lcd software controlled lcd seg key9 key9 ns touch key input key10 key10 ns touch key input key11 key11 ns touch key input key12 key12 ns touch key input vdd vdd pwr power supply vss vss pwr ground note: i/t: input type o/t: output type register select: indicates register which selects alternative function pwr: power st: schmitt trigger input cmos: cmos output nmos: nmos output lcd: lcd com or seg vbias output ns: non-standard input or output the pins in the table reflect that of the package with the largest number of pins. for this reason not all pins may exist on all package types. rev. 1.00 10 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver absolute maximum ratings supply voltage ...............................................................................................v ss 0.3v to v ss +6.0v storage temperature ................................................................................................. 50 cto125 c input voltage .................................................................................................v ss 0.3v to v dd +0.3v operating temperature .................................................................................................. 40 cto85 ci ol total .......................................................................................................................... ........80ma i oh total .................................................................................................................................. 80ma total power dissipation .........................................................................................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum rat - ings may cause substantial damage to the device. functional operation of this device at other condi - tions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage (hirc) f sys =8mhz v lvr 5.5 v f sys =12mhz 2.7 5.5 v f sys =16mhz 4.5 5.5 v i dd1 operating current (hirc), (f sys =f h ) 3v no load, f h =8mhz, wdt enable 1.2 1.8 ma 5v 2.7 4.1 ma 3v no load, f h =12mhz, wdt enable 1.9 2.9 ma 5v 4.2 6.3 ma 5v no load, f h =16mhz, wdt enable 5.6 8.4 ma i dd2 operating current (lirc), (f sys =f l ) 3v no load, f l =32khz, wdt enable 15 30 a 5v 30 50 a i idle0 idle0 mode standby current 3v no load, lvr disable 1.5 3.0 a 5v 3.0 6.0 a i idle1 idle1 mode standby current 3v no load, lvr disable, f sys =12mhz on 0.9 1.4 ma 5v 1.6 2.4 ma i sleep sleep1 mode standby current 3v no load, lvr disable 1.5 3.0 a 5v 2.5 5.0 a v il input low voltage for i/o ports or input pins 5v 0 1.5 v 0 0.2v dd v v ih input high voltage for i/o ports or input pins 5v 3.5 5.0 v 0.8v dd v dd v v lvr lvr voltage level lvr enable 5% 2.55 +5% v v ol1 output low voltage i/o port 3v i ol =9ma 0.3 v 5v i ol =20ma 0.5 v bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 11 february 1, 2011 symbol parameter test conditions min. typ. max. unit v dd conditions v ol2 output low voltage i/o port (pb) (high current enable) 3v i ol =18ma 0.3 v 5v i ol =40ma 0.5 v v oh1 output high voltage i/o port 3v i oh =3.2ma 2.7 v 5v i oh =7.4ma 4.5 v v oh2 output high voltage i/o port (pa, pe) (high current enable) 3v i oh =6.4ma 2.7 v 5v i oh =15.0ma 4.5 v v lvr lvr voltage level lvr enable, 2.55v option 5% 2.55 +5% v v lvd lvd voltage level lvden=1, v lvd =2.0v 5% 2.00 +5% v lvden=1, v lvd =2.2v 5% 2.20 +5% v lvden=1, v lvd =2.4v 5% 2.40 +5% v lvden=1, v lvd =2.7v 5% 2.70 +5% v lvden=1, v lvd =3.0v 5% 3.00 +5% v lvden=1, v lvd =3.3v 5% 3.30 +5% v lvden=1, v lvd =3.6v 5% 3.60 +5% v lvden=1, v lvd =4.2v 5% 4.20 +5% v i lv additional power consumption if lvd is used normal or slow mode 25 a idle or sleep mode 15 30 a iscom scom operating current 5v isel[1:0]=00 17.5 25.0 32.5 a isel[1:0]=01 35 50 65 a isel[1:0]=10 70 100 130 a isel[1:0]=11 140 200 260 a isseg sseg operating current 5v isel[1:0]=00 17.5 25.0 32.5 a isel[1:0]=01 35 50 65 a isel[1:0]=10 70 100 130 a isel[1:0]=11 140 200 260 a vssom voltage for lcd scom 5v 1/3 v dd 3% 0.33 +3% v dd 2/3 v dd 3% 0.67 +3% v dd vsseg voltage for lcd sseg 5v 1/3 v dd 3% 0.33 +3% v dd 2/3 v dd 3% 0.67 +3% v dd r ph pull-high resistance for i/o ports 3v 20 60 100 k 5v 10 30 50 k rev. 1.00 12 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver ta=25 c a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f cpu operating clock v lvr ~5.5v dc 8 mhz 2.7v~5.5v dc 12 mhz 4.5v~5.5v dc 16 mhz f hirc system clock (hirc) 3v/5v ta=25c 2% 8 +2% mhz 3v/5v ta=25c 2% 12 +2% mhz 5v ta=25c 2% 16 +2% mhz 3v/5v ta=0~70c 4% 8 +3% mhz 3v/5v ta=0~70c 4% 12 +3% mhz 5v ta=0~70c 4% 16 +3% mhz 2.5v~ 4.0v ta=0~70c 9% 8 +6% mhz 3.0v~ 5.5v ta=0~70c 5% 8 +12% mhz 2.7v~ 4.0v ta=0~70c 9% 12 +5% mhz 3.0v~ 5.5v ta=0~70c 5% 12 +11% mhz 4.5v~ 5.5v ta=0~70c 5% 16 +5% mhz 2.5v~ 4.0v ta= 40c~85c 12% 8 +6% mhz 3.0v~ 5.5v ta= 40 c~85c 8% 8 +12% mhz 2.7v~ 4.0v ta= 40c~85c 13% 12 +5% mhz 3.0v~ 5.5v ta= 40c~85c 8% 12 +11% mhz 4.5v~ 5.5v ta= 40c~85c 7% 16 +5% mhz f lirc system clock (lirc) 5v 10% 32 +10% khz 2.2v~ 5.5v ta=40c~+85c 50% 32 +60% khz f timer timer input pin frequency 1 f sys t int interrupt pulse width 1 s t lvr low voltage width to reset 60 120 240 s t lvd low voltage width to interrupt 180 240 360 s t lvds lvdo stable time 15 s t eerd eeprom read time 24 t sys t eewr eeprom write time 24ms t sst system start-up timer period (wake-up from halt) f sys =hirc 15~16 t sys f sys =lirc 1~2 note: 1. t sys =1/f sys 2. to maintain the accuracy of the internal hirc oscillator frequency, a 0.1 f decoupling capacitor should be connected between vdd and vss and located as close to the device as possible. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 13 february 1, 2011 power-on reset characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v por vdd start voltage to ensure power-on reset 100 mv r por ac vdd raising rate to ensure power-on reset 0.035 v/ms t por minimum time for vdd stays at v por to ensure power-on reset 1 ms oscillator temperature/frequency characteristics the following characteristic graphics depicts typical oscillator behavior. the data presented here is a statistical summary of data gathered on units from different lots over a period of time. this is for information only and the figures were not tested during manufacturing. in some of the graphs, the data exceeding the specified operating range are shown for information purposes only. the device will operate properly only within the specified range. rev. 1.00 14 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver % & & % % & & internal rc -- 8mhz (3v) 7.300 7.400 7.500 7.600 7.700 7.800 7.900 8.000 8.100 8.200 8.300 -60 -40 -20 0 20 40 60 80 100 120 140 ta(c) f sys (mhz) 2.5v 2.7v 3.0v 4.0v $ < = bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 15 february 1, 2011 internal rc -- 8mhz (5v) 7.400 7.600 7.800 8.000 8.200 8.400 8.600 8.800 -60 -40 -20 0 20 40 60 80 100 120 140 ta(c) f sys (mhz) 3.0v 4.0v 4.5v 4.75v 5.0v 5.25v 5.5v $ < = internal rc -- 12mhz (3v) 10.800 11.000 11.200 11.400 11.600 11.800 12.000 12.200 12.400 -60 -40 -20 0 20 40 60 80 100 120 140 ta (c) f sys (mhz) 2.7v 3.0v 4.0v $ < = rev. 1.00 16 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver internal rc -- 12mhz (5v) 11.400 11.600 11.800 12.000 12.200 12.400 12.600 12.800 13.000 -60 -40 -20 0 20 40 60 80 100 120 140 ta(c) f sys (mhz) 3.0v 4.0v 4.5v 4.75v 5.0v 5.25v 5.5v internal rc -- 16mhz (5v) 15.300 15.400 15.500 15.600 15.700 15.800 15.900 16.000 16.100 16.200 16.300 16.400 -60 -40 -20 0 20 40 60 80 100 120 140 ta(c) f sys (mhz) 4.5v 4.75v 5.0v 5.25v 5.5v $ < = $ < = system architecture a key factor in the high-performance features of the holtek range of microcontroller is attributed to their internal system architecture. the range of devices take advantage of the usual features found within risc microcontroller providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o control system with maximum reliability and flexibility. this makes the device suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a high or low speed oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 17 february 1, 2011 $ > $ < = ? $ > $ < . = $ > $ < @ . = ? $ > $ < = $ > $ < @ / = ? $ > $ < @ . = @ . @ / a : < $ ) = $ ) $ . $ $ ) $ / $ ) $ 1 $ ) $ 0 ' system clocking and pipelining $ > $ . ? $ > $ . $ > $ / $ ' . / 1 0 5 4 & " * : b % $ * c 6 . / ( 8 * " " $ & " * : " $ 6 . / ( 8 b b ; ? $ > $ / $ > $ 1 $ > $ 4 ? $ > $ 4 $ > $ 3 instruction fetching for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non-consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overflow, the first program counter save in the stack will be lost. device stack levels bs85b12-3 4 BS85C20-3 8 rev. 1.00 18 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver $ ) $ " d $ . ) $ " d $ / ) $ " d $ 1 ) $ " d $ ; ' $ a $ ) ) , $ a $ ) arithmetic and logic unit alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. the alu supports the following functions: arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations: and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti flash program memory the program memory is the location where the user code or program is stored. for this device series the program memory is flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. by using the appropriate programming tools, these flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. structure the program memory has a capacity of 2k 15 bits or 4k 15 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by a separate table pointer register. device capacity bs85b12-3 2kx15 BS85C20-3 4kx15 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 19 february 1, 2011 - - - 0 ( ' % . 5 $ - 3 ( - - - - ( ' % . 5 $ - ( flash program memory structure special vectors within the program memory, certain locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. look-up table any location within the program memory can be defined as a look-up table where programmers can store fixed data. to use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, tblp and tbhp. these registers define the total address of the look-up table. after setting up the table pointer, the table data can be retrieved from the program memory using the tabrd[m] or tabrdl[m] instructions, respectively. when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as 0 . the accompanying diagram illustrates the addressing data flow of the look-up table. table program example the following example using the bs85b12-3 shows how the table pointer and table data is defined and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is 700h which refers to the start address of the last page within the 2k words program memory of the device. the table pointer is setup here to have an initial value of 06h . this will ensure that the first data read from the data table will be at the program memory address 706h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the first address of the present page if the tabrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrd [m] instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. rev. 1.00 20 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver $ , " ( ! $ ( $ , " # $ , , " $ & * . 5 $ " $ ' $ , ( $ tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address mov tblp,a ; is referenced mov a,07h ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at ; program memory address 706h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at ; program memory address 705h transferred to tempreg2 and tblh in ; this example the data 1ah is transferred to tempreg1 and data ; 0fh to register tempreg2 : : org 700h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : in circuit programming the provision of flash type program memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in-circuit using a 5-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. the holtek flash mcu to writer programming pin correspondence table is as follows: holtek writer device pin description pin name pin name sdata pa0 serial address and data -- read/write sclk pa2 address and data serial clock input vpp pa7 reset input vdd vdd power supply (5.0v) vss vss ground the program memory and eeprom data memory can both be programmed serially in-circuit using this 5-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two additional lines are required for the power supply and one line for the reset. the technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 21 february 1, 2011 during the programming process the pa7 pin will be held low by the programmer disabling the normal operation of the microcontroller and taking control of the pa0 and pa2 i/o pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins. ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the first of these is an area of ram, known as the special function data memory. here are located registers which are necessary for correct operation of the device. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. device capacity bank 0 bank 1 bank 2 bs85b12-3 2568 80h~ffh 80h~ffh BS85C20-3 3848 80h~ffh 80h~ffh 80h~ffh general purpose data memory the second area of data memory is known as the general purpose data memory, which is reserved for general purpose use. all locations within this area are read and write accessible under program control. the overall data memory is subdivided into two or three banks. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the different data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for all devices is the address 00h. rev. 1.00 22 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver e e e % & & % & * * " + % $ $ * - * / % * 3 % & & $ ! $ note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf. special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specified. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers mp0, mp1 two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according to bp register. direct addressing can only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. note that for this series of devices, the memory pointers, mp0 and mp1, are both 8-bit registers and used to access the data memory together with their corresponding indirect addressing registers iar0 and iar1. the following example shows how to clear a section of four data memory locations already defined as locations adres1 to adres4. indirect addressing program example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with first ram address mov mp0,a ; setup memory pointer with first ram address loop: clr iar0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specific ram addresses. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 23 february 1, 2011 rev. 1.00 24 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver - - ( - . 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special function data memory is not affected by the bank selection, which means that the special function registers can be accessed from within any bank. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. accessing data from banks other than bank 0 must be implemented using indirect addressing. bp register -- bs85b12-3 b i t76543210 name dmbp0 r/w r/w por 0 bit 7~1 unimplemented, read as 0 bit 0 dmbp0 : select data memory banks 0: bank 0 1: bank 1 bp register -- BS85C20-3 b i t76543210 name dmbp0 dmbp0 r/w r/w r/w por 00 bit 7~2 unimplemented, read as 0 bit 1~0 dmbp1, dmbp0 : select data memory banks 00: bank 0 01: bank 1 10: bank 2 11: undefined bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 25 february 1, 2011 - ( ( - ( ( , ) $ - , ) $ - , ) $ . , ) $ . , ) $ / general purpose data memory accumulator acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specified program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers tblp, tbhp, tblh these three special function registers are used to control operation of the look-up table which is stored in the program memory. tblp and tbhp are the table pointer and indicates the location where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defined location. status register status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, operations related to the status register may give different results due to the different instruction operations. the to flag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt instruction. the pdf flag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. rev. 1.00 26 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. status register b i t76543210 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 00xxxx x unknown bit 7, 6 unimplemented, read as 0 bit 5 to : watchdog time-out flag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 pdf : power down flag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov : overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero flag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 27 february 1, 2011 eeprom data memory the devices contain an area of internal eeprom data memory. eeprom, which stands for electrically erasable programmable read only memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. by incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. the availability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is 64 8or128 8 bits for this series of devices. unlike the program memory and ram data memory, the eeprom data memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. read and write operations to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. device capacity address bs85b12-3 648 00h ~ 3fh BS85C20-3 1288 00h ~ 7fh eeprom registers three registers control the overall operation of the internal eeprom data memory. these are the address register, eea, the data register, eed and a single control register, eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same was as any other special function register. the eec register however, being located in bank1, cannot be addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register, iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must first be set to the value 40h and the bank pointer register, bp, set to the value, 01h, before any operations on the eec register are executed. eeprom register list bs85b12-3 name bit 76543210 eea d5 d4 d3 d2 d1 d0 eed d7 d6 d5 d4 d3 d2 d1 d0 eec wren wr rden rd BS85C20-3 name bit 76543210 eea d6 d5 d4 d3 d2 d1 d0 eed d7 d6 d5 d4 d3 d2 d1 d0 eec wren wr rden rd rev. 1.00 28 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver eea register bs85b12-3 b i t76543210 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por xxxxxx x unknown bit 7, 6 unimplemented, read as 0 bit 5~0 data eeprom address data eeprom address bit 5~bit 0 BS85C20-3 b i t76543210 name d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w por xxxxxxx x unknown bit 7 unimplemented, read as 0 bit 6~0 data eeprom address data eeprom address bit 6~bit 0 eec register b i t76543210 name wren wr rden rd r/w r/w r/w r/w r/w por 0000 bit 7~4 unimplemented, read as 0 bit 3 wren : data eeprom write enable 0: disable 1: enable this is the data eeprom write enable bit which must be set high before data eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom write control 0: write cycle has finished 1: activate a write cycle this is the data eeprom write control bit and when set high by the application program will activate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has finished. setting this bit high will have no effect if the wren has not first been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero will inhibit data eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has finished 1: activate a read cycle this is the data eeprom read control bit and when set high by the application program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has finished. setting this bit high will have no effect if the rden has not first been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 29 february 1, 2011 eed register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o rxxxxxxxx x unknown bit 7~0 data eeprom data data eeprom data bit 7~bit 0 reading data from the eeprom to read data from the eeprom, the read enable bit, rden, in the eec register must first be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register. if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle terminates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register. the data will remain in the eed register until another read or write operation is executed. the application program can poll the rd bit to determine when the data is valid for reading. writing data to the eeprom the eeprom address of the data to be written must first be placed in the eea register and the data placed in the eed register. to write data to the eeprom, the write enable bit, wren, in the eec register must first be set high to enable the write function. after this, the wr bit in the eec register must be immediately set high to initiate a write cycle. these two instructions must be executed consecutively. the global interrupt bit emi should also first be cleared before implementing any write operations, and then set again after the write cycle has started. note that setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has finished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on the write enable bit in the control register will be cleared preventing any write operations. also at power-on the bank pointer, bp, will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the write enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must first be enabled by setting the dee bit in the relevant interrupt register. however as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must also be set. when an eeprom write cycle ends, the def request flag and its associated multi-function interrupt request flag will both be set. if the global, eeprom and multi-function interrupts are enabled and the stack is not full, a jump to the associated multi-function interrupt vector will take place. when the interrupt is serviced only the multi-function interrupt flag will be automatically reset, the eeprom interrupt flag must be manually reset by the application program. more details can be obtained in the interrupt section. rev. 1.00 30 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensuring that the write enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly. the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. programming examples reading data from the eeprom polling method mov a, eeprom_adres ; user defined address mov eea, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a set iar1.1 ; set rden bit, enable read operations set iar1.0 ; start read cycle - set rd bit back: sz iar1.0 ; check for read cycle end jmp back clr iar1 ; disable eeprom read/write clr bp mov a, eedata ; move read data to register mov read_data, a writing data to the eeprom polling method clr emi mov a, eeprom_adres ; user defined address mov eea, a mov a, eeprom_data ; user defined data mov eed, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a set iar1.3 ; set wren bit, enable write operations set iar1.2 ; start write cycle - set wr bit - executed immediately ; after set wren bit set emi back: sz iar1.2 ; check for write cycle end jmp back clr iar1 ; disable eeprom read/write clr bp bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 31 february 1, 2011 oscillator various oscillator options offer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of configuration options and registers. oscillator overview the devices include two internal oscillators, a low speed oscillator and high speed oscillator. both can be chosen as the clock source for the main system clock however the slow speed oscillator is also used as a clock source for other functions such as the watchdog timer, time base and timer modules. both oscillators require no external components for their implementation. all oscillator options are selected using registers. the high speed oscillator provides higher performance but carries with it the disadvantage of higher power requirements, while the opposite is of course true for the low speed oscillator. with the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimise the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. internal high speed hirc 8, 12 or 16mhz internal low speed lirc 32khz oscillator types system clock configurations there are two methods of generating the system clock, a high speed internal clock source and low speed internal clock source. the high speed oscillator is an internal 8mhz, 12mhz or 16mhz rc oscillator while the low speed oscillator is an internal 32khz rc oscillator. both oscillators are fully integrated and do not require external components. selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2 ~ cks0 bits in the smod register allowing the system clock to be dynamically selected. internal high speed rc oscillator hirc the internal high speed rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has a power on default frequency of 8 mhz but can be selected to be either 8mhz, 12mhz or 16mhz using the hircs1 and hircs0 bits in the ctrl register. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. rev. 1.00 32 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver ctrl register b i t76543210 name hircs1 hircs0 d1 d0 r/w r/w r/w r/w r/w por 00 00 x unknown bit 7, 6 unimplemented, read as 0 bit 5, 4 hircs1, hircs0 : high frequency clock select 00: 8mhz 01: 16mhz 10: 12mhz 11: 8mhz bit 3, 2 unimplemented, read as 0 bit 1, 0 d1, d0 : these bits must be set to the binary value 00 internal low speed rc oscillator lirc the internal 32khz system oscillator is the low frequency oscillator. it is a fully integrated rc oscillator with a typical frequency of 32khz at 5v, requiring no external components for its implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. after power on this lirc oscillator will be permanently enabled; there is no provision to disable the oscillator using register bits. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 33 february 1, 2011 operating modes and system clocks present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. the fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. as holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the main system clock, can come from either a high frequency, f h , or low frequency, f l , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register. both the high and low speed system clocks are sourced from internal rc oscillators. rev. 1.00 34 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver ( ( f . / ( f . 4 ( f ( $ ' $ 1 / ) ( f $ a ( a : a " ( $ ' $ ) $ ( - c $ ( . $ ) $ + - g + / $ 4 $ a ( a " " 1 / ) ( f " # $ ' $ $ ! h a ( $ $ a " ! h ( " + $ $ # ) $ ! h , + $ a : 0 $ , $ - $ , $ . a " system clock configurations control register a single register, smod, is used for overall control of the internal clocks within the device. smod register b i t76543210 name cks2 cks1 cks0 d4 lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 00000011 bit 7~5 cks2~cks0 : the system clock selection when hlclk is 0 000: f l (f lirc ) 001: f l (f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which is lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 undefined bit these bits can be read or written by user software program. bit 3 lto : low speed system oscillator ready flag 0: not ready 1: ready this is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset. bit 2 hto : high speed system oscillator ready flag 0: not ready 1: ready this is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. this flag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this flag will always be read as 1 by the application program after device power-on. the flag will be low when in the sleep or idle0 mode but after a wake-up has occurred, the flag will change to a high level after 15~16 clock cycles. bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the halt instruction is executed. if this bit is high, when a halt instruction is executed the device will enter the idle mode. in the idle1 mode the cpu will stop running but the system clock will continue to keep the peripheral functions operational, if fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a halt instruction is executed. bit 0 hlclk : system clock selection 0: f h /2~f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2~f h /64 or f l clock will be selected. when system clock switches from the f h clock to the f l clock and the f h clock will be automatically switched off to conserve power. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 35 february 1, 2011 system operation modes there are five different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. there are two modes allowing normal operation of the microcontroller, the normal mode and slow mode. the remaining three modes, the sleep, idle0 and idle1 mode are used when the microcontroller cpu is switched off to conserve power. operation mode description cpu f sys f lirc f tbc normal mode on f h ~f h /64 on on slow mode on f l on on idle0 mode off off on on idle1 mode off on on on sleep mode off off on off normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator. the high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~lcks0 and hlclk bits in the smod register. although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally although now with the slow speed clock source. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the high speed clock is off. sleep mode the sleep mode is entered when a halt instruction is executed and when the idlen bit in the smod register is low. in the sleep mode the cpu will be stopped however as the f lirc oscillator continues to run the watchdog timer will continue to operate. idle0 mode the idle0 mode is entered when a halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the wdtc register is low. in the idle0 mode the system oscillator the system oscillator will be stopped and will therefore be inhibited from driving the cpu. idle1 mode the idle1 mode is entered when a halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the wdtc register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be the high speed or low speed system oscillator. rev. 1.00 36 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver operating mode switching the device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. in this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the halt instruction. when a halt instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the wdtc register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f hirc , to the clock source, f hirc /2~f hirc /64 or f lirc . if the clock is from f hirc , the high speed clock source will stop running to conserve power. when this happens it must be noted that the f hirc /16 and f hirc /64 internal clock sources will also stop running. the accompanying flowchart shows what happens when the device moves between the various operating modes. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 37 february 1, 2011 # $ % a : i a ( g a ( 4 0 a ( $ ! $ a : $ a " $ & $ % & ( * " $ $ $ ? ! $ ' & " ; i . : ; i . a : $ a " $ & $ % & ( * " $ $ $ ? ! $ ' & " ; i . : ; i - a : $ a a a " $ & $ % ' a : i a " a " $ ! $ a : $ a " $ a ( $ a a & $ % & & ( * " $ $ $ ? a : $ a a ! $ ' & " ; i - a " $ & $ normal mode to slow mode switching when running in the normal mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to 0 and set the cks2~cks0 bits to 000 or 001 in the smod register. this will then use the low speed system oscillator which will consume less power. users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode clock is sourced from the lirc oscillator. slow mode to normal mode switching in slow mode the system uses the lirc low speed system oscillator. to switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to 1 or hlclk bit is 0 , but cks2~cks0 is set to 010 , 011 , 100 , 101 , 110 or 111 .asa certain amount of time will be required for the high frequency clock to stabilise, the status of the hto bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. entering the sleep mode there is only one way for the device to enter the sleep mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 0 . when this instruction is executed under the conditions described above, the following will occur: the system clock will be stopped and the application program will stop at the halt instruction, but the f lirc clock will be on. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting. the i/o ports will maintain their present conditions. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. rev. 1.00 38 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver " $ " $ & " - $ & " . $ ; * " $ + / $ g $ + - $ i $ - - ? , $ j ( " " + $ i $ - & " ; $ i $ - ( * " $ $ $ ? & " ; $ i $ . c $ : ; i - ( * " $ $ $ ? & " ; $ i $ . c $ : ; i . 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( * " $ $ $ ? entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in wdtc register equal to 0 . when this instruction is executed under the conditions described above, the following will occur: the system clock will be stopped and the application program will stop at the halt instruction, but the time base clock and f lirc clock will be on. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting. the i/o ports will maintain their present conditions. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in wdtc register equal to 1 . when this instruction is executed under the with conditions described above, the following will occur: the system clock and f lirc clock will be on and the application program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting. the i/o ports will maintain their present conditions. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have different package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 39 february 1, 2011 wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: an external reset an external falling edge on port a a system interrupt a wdt overflow if the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a wdt overflow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other flags remain in their original status. each pin on port a can be setup using the pawu register to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up occurs, the program will resume execution at the instruction following the halt instruction. if the system is woken up by an interrupt, then two possible situations may occur. the first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the halt instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled. system oscillator wake-up time (sleep mode) wake-up time (idle0 mode) wake-up time (idle1 mode) hirc 15~16 hirc cycles 1~2 hirc cycles lirc 1~2 lirc cycles 1~2 lirc cycles wake-up times programming considerations the high speed and low speed oscillators both use the same sst counter. for example, if the system is woken up from the sleep mode the hirc oscillator needs to start-up from an off state. if the device is woken up from the sleep mode to the normal mode, the high speed system oscillator needs an sst period. the device will execute the first instruction after hto is high. rev. 1.00 40 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the watchdog timer clock source is provided by the internal low speed oscillator, f lirc . the watchdog timer source clock is then subdivided by a ratio of 2 8 to 2 15 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v. however, it should be noted that this specified internal clock period can vary with vdd, temperature and process variations. watchdog timer control register a single register, wdtc, controls the required timeout period. wdtc register b i t76543210 name fsyson ws2 ws1 ws0 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por01111010 bit 7 fsyson:f sys control in idle mode 0: disable 1: enable bit 6~4 ws2, ws1, ws0 : wdt time-out period selection 000: 256/f lirc 001: 512/f lirc 010: 1024/f lirc 011: 2048/f lirc 100: 4096/f lirc 101: 8192/f lirc 110: 16384/f lirc 111: 32768/f lirc these three bits determine the division ratio of the watchdog timer source clock, which in turn determines the timeout period. bit 3~0 undefined bit these bits can be read or written by user software program. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 41 february 1, 2011 watchdog timer operation in these devices the watchdog timer supplied by the f lirc oscillator and is therefore always on. the watchdog timer operates by providing a device reset when its timer overflows. this means that in the application program and during normal operation the user has to strategically clear the watchdog timer before it overflows to prevent the watchdog timer from executing a reset. this is done using the clear watchdog instructions. if the program malfunctions for whatever reason, jumps to an unkown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the watchdog timer will overflow and reset the device. under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the sleep or idle mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the watchdog timer. the first is an external hardware reset, the second is using the watchdog timer software clear instructions and the third is via a halt instruction. the watchdog timer is cleared using a single clr wdt instruction. the maximum time out period is when the 2 15 division ratio is selected. as an example, with the lirc oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 2 15 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration. rev. 1.00 42 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver ! " # $ % " & ! & ' ' ( ) ! " " watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is first applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. after this power-on reset, certain important internal registers will be set to defined states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are several ways in which a microcontroller reset can occur, through events occurring both internally and externally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. as well as ensuring that the program memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. low voltage reset lvr if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally. the lvr includes the following specifications: for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for greater than the value t lvr specified in the a.c. characteristics. if the low voltage state does not exceed t lvr , the lvr will ignore it and will not perform a reset function. one of a range of specified voltage values for v lvr can be selected using configuration options. the lvr function is permanently on in these devices. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 43 february 1, 2011 % & & $ - > 2 $ % & & & $ @ $ & $ @ $ note: t rstd is power-on delay, typical time=100ms power-on reset timing chart " % $ & $ @ $ note: t rstd is power-on delay, typical time=100ms low voltage reset timing chart watchdog time-out reset during normal operation the watchdog time-out reset during normal operation is the same as a hardware power-on reset except that the watchdog time-out flag to will be set to 1 . watchdog time-out reset during sleep or idle mode the watchdog time-out reset during sleep or idle mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to 0 and the to flag will be set to 1 . refer to the a.c. characteristics for t sst details. note: the t sst is 15~16 clock cycles if the system clock source is provided by hirc. the t sst is 1~2 clock for lirc. reset initial conditions the different types of reset described affect the reset flags in different ways. these flags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the sleep or idle mode function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 power-on reset u u lvr reset during normal or slow mode operation 1 u wdt time-out reset during normal or slow mode operation 1 1 wdt time-out reset during idle or sleep mode operation note: u stands for unchanged the following table indicates the way in which the various components of the microcontroller are af - fected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer modules timer counter will be turned off input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack rev. 1.00 44 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver & $ @ $ & $ $ note: t rstd is power-on delay, typical time=100ms wdt time-out reset during normal operation timing chart & $ $ wdt time-out reset during sleep or idle timing chart the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will reflect the situation for the larger package type. register power-on reset lvr reset wdt time-out (normal operation) wdt time-out (idle or sleep) mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu bp 0 0 0 u bp 00 00 00 uu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxx xxxx uuu uuuu uuu uuuu uuu uuuu tbhp xxx uuu uuu uuu tbhp xxxx uuuu uuuu uuuu status 00 xxxx uu uuuu 1u uuuu 11 uuuu smod 0000 0011 0000 0011 0000 0011 uuuu uuuu lvdc 00 000 00 000 00 000 uu uuu integ 0000 0000 0000 uuuu wdtc 0111 1010 0111 1010 0111 1010 uuuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu intc0 000 0000 000 0000 000 0000 uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc2 0000 0000 0000 0000 0000 0000 uuuu uuuu intc3 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi0 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi1 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi2 000 000 000 000 000 000 uuu uuu mfi3 0000 0000 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu 00 0000 00 0000 00 0000 uu uuuu pbpu 0000 0000 0000 0000 0000 0000 uuuu uuuu bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 45 february 1, 2011 bs85b12-3 BS85C20-3 register power-on reset lvr reset wdt time-out (normal operation) wdt time-out (idle or sleep) pb 11 1111 11 1111 11 1111 uu uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 11 1111 11 1111 11 1111 uu uuuu pbc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 uuuu uuuu pdpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 uuuu uuuu pepu 00 0000 00 0000 00 0000 uu uuuu pe 11 1111 11 1111 11 1111 uu uuuu pec 11 1111 11 1111 11 1111 uu uuuu slcdc0 0000 0000 0000 0000 0000 0000 uuuu uuuu slcdc1 0000 0000 0000 0000 0000 0000 uuuu uuuu slcdc2 00 0000 00 0000 00 0000 uu uuuu slcdc2 0000 0000 0000 0000 0000 0000 uuuu uuuu slcdc3 0 00 0000 0 00 0000 0 00 0000 u uu uuuu sledc0 00 0000 00 0000 00 0000 uu uuuu sledc0 0000 0000 0000 0000 0000 0000 uuuu uuuu sledc1 0000 0000 0000 0000 0000 0000 uuuu uuuu sledc2 00 0000 00 0000 00 0000 uu uuuu mfi4 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi5 00 00 00 00 00 00 uu uu i2ctoc 0000 0000 0000 0000 0000 0000 uuuu uuuu simc0 1110 000 1110 000 1110 000 uuuu uuu simc1 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sima/simc2 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh 00 00 00 uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu rev. 1.00 46 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver bs85b12-3 BS85C20-3 register power-on reset lvr reset wdt time-out (normal operation) wdt time-out (idle or sleep) tm0ah 00 00 00 uu eea 00 0000 00 0000 00 0000 uu uuuu eea 000 0000 000 0000 000 0000 uuu uuuu eed 0000 0000 0000 0000 0000 0000 uuuu uuuu tmpc0 1001 01 1001 01 1001 01 uuuu uu tmpc1 01 01 01 uu prm0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u prm0 0000 0000 0000 0000 0000 0000 uuuu uuuu prm1 0000 0 0 0000 0 0 0000 0 0 uuuu u u prm1 0000 0000 0000 0000 0000 0000 uuuu uuuu prm2 0000 00 0000 00 0000 00 uuuu uu prm2 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c2 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh 00 00 00 uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah 00 00 00 uu tm1bl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1bh 00 00 00 uu tm2c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2dh 00 00 00 uu tm2al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2ah 00 00 00 uu ctrl 00 00 00 00 00 00 uu uu tkm016dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm016dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm0c2 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm0c3 0000 0000 0000 0000 0000 0000 uuuu uuuu bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 47 february 1, 2011 bs85b12-3 BS85C20-3 register power-on reset lvr reset wdt time-out (normal operation) wdt time-out (idle or sleep) tkm116dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm116dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm1c2 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm1c3 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm216dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm216dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm2c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm2c1 0000 0000 0000 uuuu tkm2c2 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm2c3 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm316dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm316dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm3c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm3c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm3c2 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm3c3 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm416dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm416dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm4c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm4c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm4c2 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm4c3 0000 0000 0000 0000 0000 0000 uuuu uuuu eec 0000 0000 0000 uuuu note: u stands for unchanged x stands for unknown stands for unimplemented rev. 1.00 48 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver bs85b12-3 BS85C20-3 input/output ports holtek microcontrollers offer considerable flexibility on their i/o ports. with the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names pa~pe. these i/o ports are mapped to the ram data memory with specific addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a,[m] , where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o register list bs85b12-3 register name bit 76543210 pawu d7 d6 d5 d4 d3 d2 d1 d0 papu d7 d6 d5 d4 d3 d2 d1 d0 pa d7 d6 d5 d4 d3 d2 d1 d0 pac d7 d6 d5 d4 d3 d2 d1 d0 pbpu d5 d4 d3 d2 d1 d0 pb d5 d4 d3 d2 d1 d0 pbc d5 d4 d3 d2 d1 d0 pcpu d7 d6 d5 d4 d3 d2 d1 d0 pc d7 d6 d5 d4 d3 d2 d1 d0 pcc d7 d6 d5 d4 d3 d2 d1 d0 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 49 february 1, 2011 BS85C20-3 register name bit 76543210 pawu d7 d6 d5 d4 d3 d2 d1 d0 papu d7 d6 d5 d4 d3 d2 d1 d0 pa d7 d6 d5 d4 d3 d2 d1 d0 pac d7 d6 d5 d4 d3 d2 d1 d0 pbpu d7 d6 d5 d4 d3 d2 d1 d0 pb d7 d6 d5 d4 d3 d2 d1 d0 pbc d7 d6 d5 d4 d3 d2 d1 d0 pcpu d7 d6 d5 d4 d3 d2 d1 d0 pc d7 d6 d5 d4 d3 d2 d1 d0 pcc d7 d6 d5 d4 d3 d2 d1 d0 pdpu d7 d6 d5 d4 d3 d2 d1 d0 pd d7 d6 d5 d4 d3 d2 d1 d0 pdc d7 d6 d5 d4 d3 d2 d1 d0 pepu d5 d4 d3 d2 d1 d0 pe d5 d4 d3 d2 d1 d0 pec d5 d4 d3 d2 d1 d0 pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, all i/o pins, when configured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selected using the register papu~pepu, and are implemented using weak pmos transistors. bs85b12-3: papu, pcpu registers BS85C20-3: papu, pbpu, pcpu, pdpu registers b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7~0 pxpu port bit 7~bit 0 pull-high control 0: disable 1: enable bs85b12-3: pbpu registers BS85C20-3: pepu registers b i t76543210 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 000000 bit 7~4 unimplemented, read as 0 bit 3~0 pxpu : port bit 5~bit 0 pull-high control 0: disable 1: enable rev. 1.00 50 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver port a wake-up the halt instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low. this function is especially suitable for applications that can be woken up via external switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7~5 unimplemented, read as 0 bit 4~0 pawu: port a bit 7~bit 0 wake-up control 0: disable 1: enable i/o port control register the i/o port has its own control register known as pac~pec, to control the input/output configuration. with this control register, each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o port is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1 . this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0 , the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. bs85b12-3: pac, pcc registers BS85C20-3: pac, pbc, pcc, pdc registers b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r11111111 bit 7~0 i/o port bit 7 ~ bit 0 input/output control 0: output 1: input bs85b12-3: pbc registers BS85C20-3: pec registers b i t76543210 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 001111 bit 7~4 unimplemented, read as 0 bit 3~0 pxc : port bit 5~bit 0 input/output control 0: output 1: input bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 51 february 1, 2011 pin re-mapping functions the flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. the way in which the pin function of each pin is selected is different for each function and a priority order is established where more than one pin function is selected simultaneously. additionally there are a series of prm0, prm1 and prm2 registers to establish certain pin functions. pin-remapping registers the limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. the device includes prm0, prm1, prm2 registers which can select the functions of certain pins. pin-remapping register list bs85b12-3 register name bit 76543210 prm0 scsps0 sdips0 sckps0 sdops0 prm1 int1ps int0ps tck1ps tck0ps pints0 pckps0 prm2 tp1b2ps tp1b1ps tp1b0ps tp1aps tp01ps tp00ps BS85C20-3 register name bit 76543210 prm0 scsps1 scsps0 sdips1 sdips0 sckps1 sckps0 sdops1 sdops0 prm1 int1ps int0ps tck1ps tck0ps pints1 pints0 pckps1 pckps0 prm2 tp1b2ps tp1b1ps tp1b0ps tp1aps tp21ps tp20ps tp01ps tp00ps slcdc3 tck2ps seg21en seg20en seg19en seg18en seg17en seg16en rev. 1.00 52 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver prm0 register -- bs85b12-3 b i t76543210 name scsps0 sdips0 sckps0 sdops0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 scsps0 : scs pin remapping control 0: scs on pa3 1: scs on pc3 bit 5 unimplemented, read as 0 bit 4 sdips0 : sdi/sda pin remapping control 0: sdi/sda on pa0 1: sdi/sda on pc2 bit 3 unimplemented, read as 0 bit 2 sckps0 : sck/scl pin remapping control 0: sck/scl on pa2 1: sck/scl on pc1 bit 1 unimplemented, read as 0 bit 0 sdops0 : sdo pin remapping control 0: sdo on pa7 1: sdo on pc0 prm0 register -- BS85C20-3 b i t76543210 name scsps1 scsps0 sdips1 sdips0 sckps1 sckps0 sdops1 sdops0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7~6 scsps1~scsps0 : scs pin remapping control 00: scs on pa3 01: scs on pc3 10: scs on pe2 11: undefined bit 5~4 sdips1~sdips0 : sdi/sda pin remapping control 00: sdi/sda on pa0 01: sdi/sda on pc2 10: sdi/sda on pe4 11: undefined bit 3~2 sckps1~sckps0 : sck/scl pin remapping control 00: sck/scl on pa2 01: sck/scl on pc1 10: sck/scl on pe3 11: undefined bit 1~0 sdops1~sdops0 : sdo pin remapping control 00: sdo on pa7 01: sdo on pc0 10: sdo on pe5 11: undefined bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 53 february 1, 2011 prm1 register -- bs85b12-3 b i t76543210 name int1ps int0ps tck1ps tck0ps pints0 pckps0 r/w r/w r/w r/w r/w r/w r/w p o r0000 0 0 bit 7 int1ps : int1 pin remapping control 0: int1 on pa1 1: int1 on pc5 bit 6 int0ps : int0 pin remapping control 0: int0 on pa4 1: int0 on pc4 bit 5 tck1ps : tck1 pin remapping control 0: tck1 on pa1 1: tck1 on pc5 bit 4 tck0ps : tck0 pin remapping control 0: tck0 on pa4 1: tck0 on pc4 bit 3 unimplemented, read as 0 bit 2 pints0 : pint pin remapping control 0: pint on pb5 1: pint on pc7 bit 1 unimplemented, read as 0 bit 0 pckps0 : pck pin remapping control 0: pck on pb4 1: pck on pc6 prm1 register -- BS85C20-3 b i t76543210 name int1ps int0ps tck1ps tck0ps pints1 pints0 pckps1 pckps0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7 int1ps : int1 pin remapping control 0: int1 on pa1 1: int1 on pc5 bit 6 int0ps : int0 pin remapping control 0: int0 on pa4 1: int0 on pc4 bit 5 tck1ps : tck1 pin remapping control 0: tck1 on pa1 1: tck1 on pc5 bit 4 tck0ps : tck0 pin remapping control 0: tck0 on pa4 1: tck0 on pc4 bit 3~2 pints1~pints0 : pint pin remapping control 00: pint on pb5 01: pint on pc7 10: pint on pe0 11: undefined bit 1~0 pckps1~pckps0 : pck pin remapping control 00: pck on pb4 01: pck on pc6 10: pck on pe1 11: undefined rev. 1.00 54 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver prm2 register -- bs85b12-3 b i t76543210 name tp1b2ps tp1b1ps tp1b0ps tp1aps tp01ps tp00ps r/w r/w r/w r/w r/w r/w r/w p o r0000 00 bit 7 tp1b2ps : tp1b_2 pin remapping ccontrol 0: tp1b_2 on pb4 1: tp1b_2 on pc4 bit 6 tp1b1ps : tp1b_1 pin remapping control 0: tp1b_1 on pb3 1: tp1b_1 on pc3 bit 5 tp1b0ps : tp1b_0 pin remapping control 0: tp1b_0 on pb2 1: tp1b_0 on pc2 bit 4 tp1aps : tp1a pin remapping control 0: tp1a on pb5 1: tp1a on pc5 bit 3~2 unimplemented, read as 0 bit 1 tp01ps: tp0_1 pin remapping control 0: tp0_1 on pb1 1: tp0_1 on pc1 bit 0 tp00ps : tp0_0 pin remapping control 0: tp0_0 on pb0 1: tp0_0 on pc0 prm2 register -- BS85C20-3 b i t76543210 name tp1b2ps tp1b1ps tp1b0ps tp1aps tp21ps tp20ps tp01ps tp00ps r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7 tp1b2ps : tp1b_2 pin remapping control 0: tp1b_2 on pb4 1: tp1b_2 on pc4 bit 6 tp1b1ps : tp1b_1 pin remapping control 0: tp1b_1 on pb3 1: tp1b_1 on pc3 bit 5 tp1b0ps : tp1b_0 pin remapping control 0: tp1b_0 on pb2 1: tp1b_0 on pc2 bit 4 tp1aps : tp1a pin remapping coontrol 0: tp1a on pb5 1: tp1a on pc5 bit 3 tp21ps : tp2_1 pin remapping coontrol 0: tp2_1 on pb2 1: tp2_1 on pe2 bit 2 tp20ps : tp2_0 pin remapping coontrol 0: tp2_0 on pb1 1: tp2_0 on pe1 bit 1 tp01ps : tp0_1 pin remapping coontrol 0: tp0_1 on pb1 1: tp0_1 on pc1 bit 0 tp00ps : tp0_0 pin remapping coontrol 0: tp0_0 on pb0 1: tp0_0 on pc0 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 55 february 1, 2011 slcdc3 register -- BS85C20-3 b i t76543210 name tck2ps seg21en seg20en seg19en seg18en seg17en seg16en r/w r/w r/w r/w r/w r/w r/w r/w por 0 000000 bit 7 tck2ps: tck2 pin remapping control 0: tck2 on pc6 1: tck2 on pd0 bit 6 unimplemented, read as 0 bit 5~0 described elsewhere i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown. programming considerations within the user program, one of the first things to consider is port initialisation. after a reset, all of the i/o data and port control register will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control register, pac~pec, is then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data register, pa~pe, is first programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. rev. 1.00 56 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver % & & ! h ) ' $ $ ) ' $ & $ & k + & k + $ , & $ , $ $ ' $ $ $ $ & $ & $ , $ ' k k ) ' ( * $ generic input/output structure timer modules tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. to implement time related functions each device includes several timer modules, abbreviated to the name tm. the tms are multi-purpose timing units and serve to provide operations such as timer/counter, input capture, compare match output and single pulse output as well as being the functional unit for the generation of pwm signals. each of the tms has either two or three individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and flexible range of features. the common features of the different tm types are described here with more detailed information provided in the individual compact, standard and enhanced tm sections. introduction the devices contain from two to three tms depending upon which device is selected with each tm having a reference name of tm0, tm1 and tm2. each individual tm can be categorised as a certain type, namely compact type tm, standard type tm or enhanced type tm. although similar in nature, the different tm types vary in their feature complexity. the common features to all of the compact, standard and enhanced tms will be described in this section, the detailed operation regarding each of the tm types will be described in separate sections. the main features and differences between the three types of tms are summarised in the accompanying table. function ctm stm etm timer/counter i/p capture compare match output pwm channels 1 1 2 single pulse output 12 pwm alignment edge edge edge & centre pwm adjustment period & duty duty or period duty or period duty or period tm function summary each device in the series contains a specific number of either compact type, standard type and en - hanced type tm units which are shown in the table together with their individual reference name, tm0~tm2. device tm0 tm1 tm2 bs85b12-3 10-bit ctm 10-bit etm BS85C20-3 10-bit ctm 10-bit etm 10-bit stm tm name/type reference tm operation the three different types of tm offer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. when the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a tm interrupt signal will be generated which can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable clock source, which can be an internal clock or an external pin. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 57 february 1, 2011 tm clock source the clock source which drives the main counter in each tm can originate from various sources. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f tbc clock source or the external tckn pin. note that setting these bits to the value 101 will select a reserved clock input, in effect disconnecting the tm clock source. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the compact and standard type tms each have two internal interrupts, one for each of the internal comparator a or comparator p, which generate a tm interrupt when a compare match condition occurs. as the enhanced type tm has three internal comparators and comparator a or comparator b or comparator p compare match functions, it consequently has three internal interrupts. when a tm interrupt is generated it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin, is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register. this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm if selected using the tnck2~tnck0 bits. the tm input pin can be chosen to have either a rising or falling active edge. the tms each have one or more output pins with the label tpn. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must first be setup using registers. a single bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. the number of output pins for each tm type and device is different, the details are provided in the accompanying table. all tm output pin names have an _n suffix. pin names that include a _1 or _2 suffix indicate that they are from a tm with multiple output pins. this allows the tm to generate a complimentary output pair, selected using the i/o register data bits. device ctm stm etm registers bs85b12-3 tp0_0, tp0_1 tp1a, tp1b_0, tp1b_1, tp1b_2 tmpc0 BS85C20-3 tp0_0, tp0_1 tp2_0, tp2_1 tp1a, tp1b_0, tp1b_1, tp1b_2 tmpc0, tmpc1 tm output pins rev. 1.00 58 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver tm input/output pin control registers selecting to have a tm input/output or whether to retain its other shared function, is implemented using one or two registers, with a single bit in each register corresponding to a tm input/output pin. setting the bit high will setup the corresponding pin as a tm input/output, if reset to zero the pin will retain its original other function. registers device bit 76543210 tmpc0 all t1acp0 t1bcp2 t1bcp1 t1bcp0 t0cp1 t0cp0 tmpc0 BS85C20-3 t2cp1 t2cp0 tm input/output pin control registers list tmpc0 register -- all devices b i t76543210 name t1acp0 t1bcp2 t1bcp1 t1bcp0 t0cp1 t0cp0 r/w r/w r/w r/w r/w r/w r/w p o r1001 01 bit 7 t1acp0 : tp1a pin control 0: disable 1: enable bit 6 t1bcp2 : tp1b_2 pin control 0: disable 1: enable bit 5 t1bcp1 : tp1b_1 pin control 0: disable 1: enable bit 4 t1bcp0 : tp1b_0 pin control 0: disable 1: enable bit 3~2 unimplemented, read as 0 bit 1 t0cp1 : tp0_1 pin control 0: disable 1: enable bit 0 t0cp0 : tp0_0 pin control 0: disable 1: enable tmpc1 register -- BS85C20-3 b i t76543210 name t2cp1 t2cp0 r/w r/w r/w por 01 bit 7~2 unimplemented, read as 0 bit 1 t2cp1 : tp2_1 pin control 0: disable 1: enable bit 0 t2cp0 : tp2_0 pin control 0: disable 1: enable bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 59 february 1, 2011 rev. 1.00 60 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver tm0 function pin control block diagram note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input. tm2 function pin control block diagram -- BS85C20-3 only note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 61 february 1, 2011 ! ! ! ! ! ! tm1 function pin control block diagram note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input. programming considerations the tm counter registers and the capture/compare ccra and ccrb registers, being either 10-bit or 16-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. the important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra and ccrb registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way as described above, it is recommended to use the mov instruction to access the ccra and ccrb low byte registers, named tmxal and tmxbl, using the following access procedures. accessing the ccra or ccrb low byte registers without following these access procedures will result in unpredictable values. the following steps show the read and write procedures: writing data to ccrb or ccra step 1. write data to low byte tmxal or tmxbl - note that here data is only written to the 8-bit buffer. step 2. write data to high byte tmxah or tmxbh - here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. reading data from the counter registers and ccrb or ccra step 1. read data from the high byte tmxdh, tmxah or tmxbh - here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. step 2. read data from the low byte tmxdl, tmxal or tmxbl - this step reads data from the 8-bit buffer. rev. 1.00 62 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver data bus 8-bit buffer tmxdh tmxdl tmxbh tmxbl tmxah tmxal tm counter register (read only) tm ccra register (read/write) tm ccrb register (read/write) compact type tm ctm although the simplest form of the three tm types, the compact tm type still contains three operating modes, which are compare match output, timer/event counter and pwm output modes. the compact tm can also be controlled with an external input pin and can drive one or two external output pins. these two external output pins can be the same signal or the inverse signal. ctm name tm no. tm input pin tm output pin bs85b12-3 10-bit ctm 0 tck0 tp0_0, tp0_1 BS85C20-3 10-bit ctm 0 tck0 tp0_0, tp0_1 compact tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 63 february 1, 2011 " # $ % # $ % & ' ( ) * & ) + ! , ) # , ) # - , ) , ) & ) + $ . $ . " - / - - 0 1 2 1 0 1 2 1 0 3 0 3 0 4 5 6 compact type tm block diagram compact type tm register description overall operation of the compact tm is controlled using six registers. a read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmnc0 tnpau tnck2 tnck1 tnck0 tnon tnrp2 tnrp1 tnrp0 tmnc1 tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr tmndl d7 d6 d5 d4 d3 d2 d1 d0 tmndh d9 d8 tmnal d7 d6 d5 d4 d3 d2 d1 d0 tmnah d9 d8 compact tm register list (n=0) tmndl register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/wrrrrrrrr p o r00000000 bit 7~0 tmndl : tmn counter low byte register bit 7 ~ bit 0 tmn 10-bit counter bit 7 ~ bit 0 tmndh register b i t76543210 name d9 d8 r/w rr por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tmndh : tmn counter high byte register bit 1 ~ bit 0 tmn 10-bit counter bit 9 ~ bit 8 tmnal register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 tmnal : tmn ccra low byte register bit 7 ~ bit 0 tmn 10-bit ccra bit 7 ~ bit 0 rev. 1.00 64 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver tmnah register b i t76543210 name d9 d8 r/w r/w r/w por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tmn 10-bit ccra bit 9 ~ bit 8 tmnc0 register b i t76543210 name tnpau tnck2 tnck1 tnck0 tnon tnrp2 tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7 tnpau : tmn counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0 : select tmn counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: undefined 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 tnon : tmn counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specified by the tnoc bit, when the tnon bit changes from low to high. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 65 february 1, 2011 bit 2~0 tnrp2~tnrp0 : tmn ccrp 3-bit register, compared with the tmn counter bit 9~bit 7 comparator p match period 000: 1024 tmn clocks 001: 128 tmn clocks 010: 256 tmn clocks 011: 384 tmn clocks 100: 512 tmn clocks 101: 640 tmn clocks 110: 768 tmn clocks 111: 896 tmn clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counter's highest three bits. the result of this comparison can be selected to clear the internal counter if the tncclr bit is set to zero. setting the tncclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. tmnc1 register bit76543210 name tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~6 tnm1~tnm0 : select tmn operating mode 00: compare match output mode 01: undefined 10: pwm mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the tnm1 and tnm0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 tnio1~tnio0 : select tpn_0, tpn_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefined timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit in the tmnc1 register. note that the output level requested by the tnio1 and tnio0 bits must be different from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the tnon bit from low to high. rev. 1.00 66 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to change the values of the tnio1 and tnio0 bits only after the tmn has been switched off. unpredictable pwm outputs will occur if the tnio1 and tnio0 bits are changed when the tm is running bit 3 tnoc : tpn_0, tpn_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 tnpol : tpn_0, tpn_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn_0 or tpn_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 tndpx : tmn pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 tncclr : select tmn counter clear condition 0: tmn comparatror p match 1: tmn comparatror a match this bit is used to select the method which clears the counter. remember that the compact tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overflow. a counter overflow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm mode. compact type tm operating modes the compact type tm can operate in one of three operating modes, compare match output mode, pwm mode or timer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overflow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overflow. here both tnaf and tnpf interrupt request flags for the comparator a and comparator p respectively, will both be generated. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 67 february 1, 2011 if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request flag will be generated. if the ccra bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3ff hex, value, however here the tnaf interrupt request flag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when an tnaf interrupt request flag is generated after a compare match occurs from comparator a. the tnpf interrupt request flag, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place. rev. 1.00 68 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver counter value 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin time ccrp=0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart tncclr = 0; tnm [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 active high output select here tnio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnpol is high compare match output mode -- tncclr = 0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf flag 3. the output pin is reset to its initial state by a tnon bit rising edge timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 69 february 1, 2011 counter value 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin time ccra=0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart tncclr = 1; tnm [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 active high output select here tnio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnpol is high tnpf not generated no tnaf flag generated on ccra overflow output does not change compare match output mode -- tncclr = 1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf flag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf flag is not generated when tncclr=1 pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the tncclr bit has no effect on the pwm operation. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt flag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fixed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. rev. 1.00 70 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time counter cleared by ccrp pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 0; tnm [1:0] = 10 pwm duty cycle set by ccra pwm resumes operation output controlled by other pin-shared function output inverts when tnpol = 1 pwm period set by ccrp tm o/p pin (tnoc=0) pwm mode -- tndpx = 0 note: 1. here tndpx=0 -- counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0] = 00 or 01 4. the tncclr bit has no influence on pwm operation ctm, pwm mode, edge-aligned mode, t0dpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 128 256 384 512 640 768 896 1024 duty ccra if f sys = 16mhz, tm clock source is f sys /4, ccrp = 100b and ccra =128, the ctm pwm output frequency = (f sys /4)/512=f sys /2048 = 7.8125 khz, duty = 128/512 = 25%. if the duty value defined by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ctm, pwm mode, edge-aligned mode, t0dpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccra duty 128 256 384 512 640 768 896 1024 the output period is determined by the ccra register value together with the tm clock while the pwm duty cycle is defined by the ccrp register value. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 71 february 1, 2011 counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time counter cleared by ccra pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 1; tnm [1:0] = 10 pwm duty cycle set by ccrp pwm resumes operation output controlled by other pin-shared function output inverts when tnpol = 1 pwm period set by ccra tm o/p pin (tnoc=0) pwm mode -- tndpx = 1 note: 1. here tndp x=1-- counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0] = 00 or 01 4. the tncclr bit has no influence on pwm operation standard type tm stm the standard type tm contains five operating modes, which are compare match output, timer/event counter, capture input, single pulse output and pwm output modes. the standard tm can also be controlled with an external input pin and can drive one or two external output pins. ctm name tm no. tm input pin tm output pin bs85b12-3 BS85C20-3 10-bit stm 2 tck2 tp2_0, tp2_1 standard tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the standard type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers. rev. 1.00 72 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver " # $ % # $ % & ' ( ) * & ) + ! , ) # , ) # - , ) , ) & ) + 6 7 . $ . $ . " - / - - 0 1 2 1 0 1 2 1 0 3 0 3 0 4 5 6 standard type tm block diagram standard type tm register description overall operation of the standard tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. stm register list name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm2c0 t2pau t2ck2 t2ck1 t2ck0 t2on t2rp2 t2rp1 t2rp0 tm2c1 t2m1 t2m0 t2io1 t2io0 t2oc t2pol t2dpx t2cclr tm2dl d7 d6 d5 d4 d3 d2 d1 d0 tm2dh d9 d8 tm2al d7 d6 d5 d4 d3 d2 d1 d0 tm2ah d9 d8 10-bit standard tm register list tm2c0 register b i t76543210 name t2pau t2ck2 t2ck1 t2ck0 t2on t2rp2 t2rp1 t2rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 t2pau : tm2 counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t2ck2~t2ck0 : select tm2 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: undefined 110: tck2 rising edge clock 111: tck2 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 t2on : tm2 counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specified by the t2oc bit, when the t2on bit changes from low to high. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 73 february 1, 2011 bit 2~0 t2rp2~t2rp0 : tm2 ccrp 3-bit register, compared with the tm2 counter bit 9~bit 7 comparator p match period 000: 1024 tm2 clocks 001: 128 tm2 clocks 010: 256 tm2 clocks 011: 384 tm2 clocks 100: 512 tm2 clocks 101: 640 tm2 clocks 110: 768 tm2 clocks 111: 896 tm2 clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counter's highest three bits. the result of this comparison can be selected to clear the internal counter if the t2cclr bit is set to zero. setting the t2cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. tm2c1 register b i t76543210 name t2m1 t2m0 t2io1 t2io0 t2oc t2pol t2dpx t2cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~6 t2m1~t2m0 : select tm2 operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t2m1 and t2m0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t2io1~t2io0 : select tp2_0, tp2_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp2_0, tp2_1 01: input capture at falling edge of tp2_0, tp2_1 10: input capture at falling/rising edge of tp2_0, tp2_1 11: input capture disabled timer/counter mode: unused rev. 1.00 74 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t2io1 and t2io0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t2oc bit in the tm2c1 register. note that the output level requested by the t2io1 and t2io0 bits must be different from the initial value setup using the t2oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t2on bit from low to high. in the pwm mode, the t2io1 and t2io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to change the values of the t2io1 and t2io0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t2io1 and t2io0 bits are changed when the tm is running bit 3 t2oc : tp2_0, tp2_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t2pol : tp2_0, tp2_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp2_0 or tp2_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t2dpx : tm1 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t2cclr : select tm1 counter clear condition 0: tm2 comparatror p match 1: tm2 comparatror a match this bit is used to select the method which clears the counter. remember that the standard tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the t2cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overflow. a counter overflow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t2cclr bit is not used in the pwm, single pulse or input capture mode. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 75 february 1, 2011 tm2dl register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/wrrrrrrrr p o r00000000 bit 7~0 tm2dl : tm2 counter low byte register bit 7~bit 0 tm2 10-bit counter bit 7~bit 0 tm2dh register b i t76543210 name d9 d8 r/w rr por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tm2dh : tm2 counter high byte register bit 1~bit 0 tm2 10-bit counter bit 9~bit 8 tm2al register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 tm2al : tm2 ccra low byte register bit 7~bit 0 tm2 10-bit ccra bit 7~bit 0 tm2ah registe b i t76543210 name d9 d8 r/w r/w r/w por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tm2ah : tm2 ccra high byte register bit 1~bit 0 tm2 10-bit ccra bit 9~bit 8 rev. 1.00 76 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver standard type tm operating modes the standard type tm can operate in one of five operating modes, compare match output mode, pwm mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overflow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match from comparator p, the other is when the ccrp bits are all zero which allows the counter to overflow. here both tnaf and tnpf interrupt request flags for comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request flag will be generated. in the compare match output mode, the ccra can not be set to 0. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 77 february 1, 2011 counter value 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin time ccrp=0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart tncclr = 0; tnm [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 active high output select here tnio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnpol is high compare match output mode -- tncclr = 0 note: 1. with tncclr=0 a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf flag 3. the output pin is reset to itsinitial state by a tnon bit rising edge as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a tnaf interrupt request flag is generated after a compare match occurs from comparator a. the tnpf interrupt request flag, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place. timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. rev. 1.00 78 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver counter value 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin time ccra=0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart tncclr = 1; tnm [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 active high output select here tnio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnpol is high tnpf not generated no tnaf flag generated on ccra overflow output does not change compare match output mode -- tncclr = 1 note: 1. with tncclr=1 a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf flag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. a tnpf flag is not generated when tncclr=1 pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the tncclr bit has no effect on the pwm operation. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt flag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fixed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. stm, pwm mode, edge-aligned mode, t0dpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 128 256 384 512 640 768 896 1024 duty ccra if f sys = 16mhz, tm clock source is f sys /4, ccrp = 100b and ccra =128, the stm pwm output frequency = (f sys /4)/512=f sys /2048 = 7.8125 khz, duty = 128/512 = 25%. if the duty value defined by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. stm, pwm mode, edge-aligned mode, t0dpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccra duty 128 256 384 512 640 768 896 1024 the pwm output period is determined by the ccra register value together with the tm clock while the pwm duty cycle is defined by the ccrp register value. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 79 february 1, 2011 rev. 1.00 80 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time counter cleared by ccrp pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 0; tnm [1:0] = 10 pwm duty cycle set by ccra pwm resumes operation output controlled by other pin-shared function output inverts when tnpol = 1 pwm period set by ccrp tm o/p pin (tnoc=0) pwm mode -- tndpx = 0 note: 1. here tndpx=0 ?v counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0] = 00 or 01 4. the tncclr bit has no influence on pwm operation single pulse mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively and also the tnio1 and tnio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output leading edge is a low to high transition of the tnon bit, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 81 february 1, 2011 counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time counter cleared by ccra pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 1; tnm [1:0] = 10 pwmdutycycle set by ccrp pwm resumes operation output controlled by other pin-shared function output inverts when tnpol = 1 pwm period set by ccra tm o/p pin (tnoc=0) pwm mode -- tndpx = 1 note: 1. here tndpx=1 -- counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0] = 00 or 01 4. the tncclr bit has no influence on pwm operation however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a tm interrupt. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr and tndpx bits are not used in this mode. rev. 1.00 82 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver " 6 7 6 7 ' ) 1 8 # # 6 1 9 ' 9 4 ' ) 1 8 # # 6 " 9 ' 9 $ % # - 4 8 6 % : ; - - 7 6 7 $ single pulse generation counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time counter stopped by ccra pause resume counter stops by software counter reset when tnon returns high tnm [1:0] = 10 ; tnio [1:0] = 11 pulse width set by ccra output inverts when tnpol = 1 no ccrp interrupts generated tm o/p pin (tnoc=0) tckn pin software trigger cleared by ccra match tckn pin trigger auto. set by tckn pin software trigger software clear software trigger software trigger single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high 5. in the single pulse mode, tnio [1:0] must be set to 11 and can not be changed. capture input mode to select this mode bits tnm1 and tnm0 in the tmnc1 register should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tpn_0 or tpn_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnio1 and tnio0 bits in the tmnc1 register. the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpn_0 or tpn_1 pin, the present value in the counter will be latched into the ccra registers and a tm interrupt generated. irrespective of what events occur on the tpn_0 or tpn_1 pin the counter will continue to free run until the tnon bit changes from high to low. when a ccrp compare match occurs, the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tm interrupt will also be generated. counting the number of overflow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the tnio1 and tnio0 bits can select the active trigger edge on the tpn_0 or tpn_1 pin to be a rising edge, falling edge or both edge types. if the tnio1 and tnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpn_0 or tpn_1 pin, however it must be noted that the counter will continue to run. as the tpn_0 or tpn_1 pin is pin shared with other functions, care must be taken if the tm is in the input capture mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr and tndpx bits are not used in this mode. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 83 february 1, 2011 counter value yy ccrp tnon tnpau ccrp int. flag tnpf ccra int. flag tnaf ccra value time counter cleared by ccrp pause resume counter reset tnm [1:0] = 01 tm capture pin tpn_x xx counter stop tnio [1:0] value xx yy xx yy active edge active edge active edge 00 rising edge 01 falling edge 10 both edges 11 disable capture capture input mode note: 1.. tnm [1:0] = 01 and active edge set by the tnio [1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function -- tnoc and tnpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero. enhanced type tm etm the enhanced type tm contains five operating modes, which are compare match output, timer/event counter, capture input, single pulse output and pwm output modes. the enhanced tm can also be controlled with an external input pin and can drive three or four external output pins. ctm name tm no. tm input pin tm output pin bs85b12-3 10-bit etm 1 tck1 tp1a, tp1b_0, tp1b_1, tp1b_2 BS85C20-3 10-bit etm 1 tck1 tp1a, tp1b_0, tp1b_1, tp1b_2 enhanced tm operation at its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal or external clock source. there are three internal comparators with the names, comparator a, comparator b and comparator p. these comparators will compare the value in the counter with the ccra, ccrb and ccrp registers. the ccrp comparator is 3-bits wide whose value is compared with the highest 3-bits in the counter while ccra and ccrb are 10-bits wide and therefore compared with all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the enhanced type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control output pins. all operating setup conditions are selected using relevant internal registers. rev. 1.00 84 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver " # $ % # $ % & ' ( ) * & ) + ! , ) # , ) # - , ) ( < ) & ) + 6 7 . $ . $ . " - / - - 0 1 2 1 0 1 2 1 0 3 0 3 0 4 5 6 $ . $ . " - / - - # $ % , ) # 6 7 . , , , enhanced type tm block diagram enhanced type tm register description overall operation of the enhanced tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrb value. the remaining three registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm1c0 t1pau t1ck2 t1ck1 t1ck0 t1on t1rp2 t1rp1 t1rp0 tm1c1 t1am1 t1am0 t1aio1 t1aio0 t1aoc t1apol t1cdn t1cclr tm1c2 t1bm1 t1bm0 t1bio1 t1bio0 t1boc t1bpol t1pwm1 t1pwm0 tm1dl d7 d6 d5 d4 d3 d2 d1 d0 tm1dh d9 d8 tm1al d7 d6 d5 d4 d3 d2 d1 d0 tm1ah d9 d8 tm1bl d7 d6 d5 d4 d3 d2 d1 d0 tm1bh d9 d8 10-bit enhanced tm register list (if etm is tm1) 10-bit enhanced tm register list tm1c0 register -- 10-bit etm b i t76543210 name t1pau t1ck2 t1ck1 t1ck0 t1on t1rp2 t1rp1 t1rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 t1pau : tm1 counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t1ck2~t1ck0 : select tm1 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: undefined 110: tck1 rising edge clock 111: tck1 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 85 february 1, 2011 bit 3 t1on : tm1 counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specified by the t1oc bit, when the t1on bit changes from low to high. bit 2~0 t1rp2~t1rp0 : tm1 3-bit register, compared with the tm1 counter bit 9~bit 7 comparator p match period 000: 1024 tm1 clocks 001: 128 tm1 clocks 010: 256 tm1 clocks 011: 384 tm1 clocks 100: 512 tm1 clocks 101: 640 tm1 clocks 110: 768 tm1 clocks 111: 896 tm1 clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counter s highest three bits. the result of this comparison can be selected to clear the internal counter if the t1cclr bit is set to zero. setting the t1cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. tm1c1 register -- 10-bit etm b i t76543210 name t1am1 t1am0 t1aio1 t1aio0 t1aoc t1apol t1cdn t1cclr r/w r/w r/w r/w r/w r/w r/w r r/w por00000000 bit 7~6 t1am1~t1am0 : select tm1 ccra operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t1am1 and t1am0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t1aio1~t1aio0 : select tp1a output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output mode/ single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1a 01: input capture at falling edge of tp1a 10: input capture at falling/rising edge of tp1a 11: input capture disabled rev. 1.00 86 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1aio1 and t1aio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1aoc bit in the tm1c1 register. note that the output level requested by the t1aio1 and t1aio0 bits must be different from the initial value setup using the t1aoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1aio1 and t1aio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to change the values of the t1aio1 and t1aio0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t1aio1 and t1aio0 bits are changed when the tm is running bit 3 t1aoc : tp1a output control bit compare match output mode 0: initial low 1: initial high mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1apol : tp1a output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1a output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t1cdn : tm1 counter count up or down flag 0: count up 1: count down bit 0 t1cclr : select tm1 counter clear condition 0: tm1 comparator p match 1: tm1 comparator a match this bit is used to select the method which clears the counter. remember that the enhanced tm contains three comparators, comparator a, comparator b and comparator p, but only comparator a or comparator pan be selected to clear the internal counter. with the t1cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overflow. a counter overflow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the pwm, single pulse or input capture mode. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 87 february 1, 2011 tm1c2 register -- 10-bit etm b i t76543210 name t1bm1 t1bm0 t1bio1 t1bio0 t1boc t1bpol t1pwm1 t1pwm0 r/w r/w r/w r/w r/w r/w r/w r r/w por00000000 bit 7~6 t1bm1~t1bm0 : select tm1 ccrb operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t1bm1 and t1bm0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t1bio1~t1bio0 : select tp1b_0, tp1b_1, tp1b_2 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1b_0, tp1b_1, tp1b_2 01: input capture at falling edge of tp1b_0, tp1b_1, tp1b_2 10: input capture at falling/rising edge of tp1b_0, tp1b_1, tp1b_2 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1bio1 and t1bio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1boc bit in the tm1c2 register. note that the output level requested by the t1bio1 and t1bio0 bits must be different from the initial value setup using the t1boc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1bio1 and t1bio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to change the values of the t1bio1 and t1bio0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t1bio1 and t1bio0 bits are changed when the tm is running rev. 1.00 88 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver bit 3 t1boc : tp1b_0, tp1b_1, tp1b_2 output control bit compare match output mode 0: initial low 1: initial high mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1bpol : tp1b_0, tp1b_1, tb1b_2 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1b_0, tp1b_1, tp1b_2 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1~0 t1pwm1~t1pwm0 : select pwm mode 00: edge aligned 01: centre aligned, compare match on count up 10: centre aligned, compare match on count down 11: centre aligned, compare match on count up or down tm1dl register -- 10-bit etm b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/wrrrrrrrr p o r00000000 bit 7~0 tm1dl : tm1 counter low byte register bit 7~bit 0 tm1 10-bit counter bit 7~bit 0 tm1dh register -- 10-bit etm b i t76543210 name d9 d8 r/w rr por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tm1dh : tm1 counter high byte register bit 1~bit 0 tm1 10-bit counter bit 9~bit 8 tm1al register -- 10-bit etm bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 tm1al : tm1 low byte register bit 7~bit 0 tm1 10-bit ccra bit 7~bit 0 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 89 february 1, 2011 tm1ah register -- 10-bit etm b i t76543210 name d9 d8 r/w r/w r/w por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tm1ah : tm1 high byte register bit 1~bit 0 tm1 10-bit ccra bit 9~bit 8 tm1bl register -- 10-bit etm b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit7~0 tm1bl : tm1 low byte register bit 7~bit 0 tm1 10-bit ccrb bit 7~bit 0 tm1bh register -- 10-bit etm b i t76543210 name d9 d8 r/w r/w r/w por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tm1bh : tm1 high byte register bit 1~bit 0 tm1 10-bit ccrb bit 9 ~ bit 8 enhanced type tm operating modes the enhanced type tm can operate in one of five operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the tnam1 and tnam0 bits in the tmnc1, and the tnbm1 and tnbm0 bits in the tmnc2 register. etm operating mode ccra compare match output mode ccra timer/count er mode ccra pwm output mode ccra single pulse output mode ccra input capture mode ccrb compare match output mode ccrb timer/counter mode ccrb pwm output mode ccrb single pulse output mode ccrb input capture mode : permitted; : not permitted rev. 1.00 90 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver compare output mode to select this mode, bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1/tmnc2 registers should be all cleared to zero. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overflow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overflow. here both the tnaf and tnpf interrupt request flags for comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request flag will be generated. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 91 february 1, 2011 counter value 0x3ff ccrp ccra tnon tnpau tnapol ccrp int. flag tnpf ccra int. flag tnaf tpna o/p pin time ccrp=0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart tncclr = 0; tnam [1:0] = 00 output pin set to initial level low if tnaoc=0 output toggle with tnaf flag note tnaio [1:0] = 10 active high output select here tnaio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnapol is high etm ccra compare match output mode -- tncclr = 0 note: 1. with tncclr=0 a comparator p match will clear the counter 2. the tpna output pin is controlled only by the tnaf flag 3. the output pin is reset to its initial state by a tnon bit rising edge as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when an tnaf or tnbf interrupt request flag is generated after a compare match occurs from comparator a or comparator b. the tnpf interrupt request flag, generated from a compare match from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state is determined by the condition of the tnaio1 and tnaio0 bits in the tmnc1 register for etm ccra, and the tnbio1 and tnbio0 bits in the tmnc2 register for etm ccrb. the tm output pin can be selected using the tnaio1, tnaio0 bits (for the tpna pin) and tnbio1, tnbio0 bits (for the tpnb_0, tpnb_1 or tpnb_2 pins) to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a or a compare match occurs from comparator b. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnaoc or tnboc bit for tpna or tpnb_0, tpnb_1, tpnb_2 output pins. note that if the tnaio1,tnaio0 and tnbio1, tnbio0 bits are zero then no pin change will take place. rev. 1.00 92 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver counter value 0x3ff ccrp ccrb tnon tnpau tnbpol ccrp int. flag tnpf ccrb int. flag tnbf tpnb o/p pin time ccrp=0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart tncclr = 0; tnbm [1:0] = 00 output pin set to initial level low if tnboc=0 output toggle with tnbf flag note tnbio [1:0] = 10 active high output select here tnbio [1:0] = 11 toggle output select output not affected by tnbf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnbpol is high etm ccrb compare match output mode -- tncclr = 0 note: 1. with tncclr=0 a comparator p match will clear the counter 2. the tpnb output pin is controlled only by the tnbf flag 3. the output pin is reset to its initial state by a tnon bit rising edge bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 93 february 1, 2011 counter value 0x3ff ccrp ccra tnon tnpau tnapol ccrp int. flag tnpf ccra int. flag tnaf tpna o/p pin time ccra=0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart tncclr = 1; tnam [1:0] = 00 output pin set to initial level low if tnaoc=0 output toggle with tnaf flag note tnaio [1:0] = 10 active high output select here tnaio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnapol is high tnpf not generated no tnaf flag generated on ccra overflow output does not change etm ccra compare match output mode -- tncclr = 1 note: 1. with tncclr=1 a comparator a match will clear the counter 2. the tpna output pin is controlled only by the tnaf flag 3. the tpna output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf flag is not generated when tncclr=1 rev. 1.00 94 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver counter value 0x3ff ccrb ccra tnon tnpau tnbpol ccrb int. flag tnbf ccra int. flag tnaf tpnb o/p pin time ccra=0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart tncclr = 1; tnbm [1:0] = 00 output pin set to initial level low if tnboc=0 output toggle with tnbf flag note tnbio [1:0] = 10 active high output select here tnbio [1:0] = 11 toggle output select output not affected by tnbf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnbpol is high no tnaf flag generated on ccra overflow etm ccrb compare match output mode -- tncclr = 1 note: 1. with tncclr=1 a comparator a match will clear the counter 2. the tpnb output pin is controlled only by the tnbf flag 3. the tpnb output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf flag is not generated when tncclr=1 timer/counter mode to select this mode, bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1 and tmnc2 register should all be set high. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, the required bit pairs, tnam1, tnam0 and tnbm1, tnbm0 should be set to 10 respectively and also the tnaio1, tnaio0 and tnbio1, tnbio0 bits should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the tncclr bit is used to determine in which way the pwm period is controlled. with the tncclr bit set high, the pwm period can be finely controlled using the ccra registers. in this case the ccrb registers are used to set the pwm duty value (for tpnb output pins). the ccrp bits are not used and tpna output pin is not used. the pwm output can only be generated on the tpnb output pins. with the tncclr bit cleared to zero, the pwm period is set using one of the eight values of the three ccrp bits, in multiples of 128. now both ccra and ccrb registers can be used to setup different duty cycle values to provide dual pwm outputs on their relative tpna and tpnb pins. the tnpwm1 and tnpwm0 bits determine the pwm alignment type, which can be either edge or centre type. in edge alignment, the leading edge of the pwm signals will all be generated concurrently when the counter is reset to zero. with all power currents switching on at the same time, this may give rise to problems in higher power applications. in centre alignment the centre of the pwm active signals will occur sequentially, thus reducing the level of simultaneous power switching currents. interrupt flags, one for each of the ccra, ccrb and ccrp, will be generated when a compare match occurs from either the comparator a, comparator b or comparator p. the tnaoc and tnboc bits in the tmnc1 and tmnc2 register are used to select the required polarity of the pwm waveform while the two tnaio1, tnaio0 and tnbio1, tnbio0 bits pairs are used to enable the pwm output or to force the tm output pin to a fixed high or low level. the tnapol and tnbpol bit are used to reverse the polarity of the pwm output waveform. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 95 february 1, 2011 etm, pwm mode, edge-aligned mode, tncclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 128 256 384 512 640 768 896 1024 a duty ccra b duty ccrb if f sys = 16mhz, tm clock source select f sys /4, ccrp = 100b, ccra = 128 and ccrb = 256, the tp1a pwm output frequency = (f sys /4)/512=f sys /2048 = 7.8125khz, duty = 128/512 = 25%. the tp1b_n pwm output frequency = (f sys /4)/512=f sys /2048 = 7.8125khz, duty = 256/512 = 50%. if the duty value defined by ccra or ccrb register is equal to or greater than the period value, then the pwm output duty is 100%. etm, pwm mode, edge-aligned mode, tncclr=1 ccra 1 2 3 511 512 1021 1022 1023 period 1 2 3 511 512 1021 1022 1023 b duty ccrb etm, pwm mode, center-aligned mode, tncclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 256 512 768 1024 1280 1536 1792 2046 a duty (ccra2) 1 b duty (ccrb2) 1 etm, pwm mode, center-aligned mode, tncclr=1 ccra 1 2 3 511 512 1021 1022 1023 period 2 4 6 1022 1024 2042 2044 2046 b duty (ccrb2) 1 rev. 1.00 96 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 97 february 1, 2011 counter value ccrp ccra tnon tnpau tnapol ccra int. flag tnaf ccrb int. flag tnbf tpna pin (tnaoc=1) time counter cleared by ccrp pause resume stop counter restart tncclr = 0; tnam [1:0] = 10, tnbm [1:0] = 10; tnpwm [1:0] = 00 output pin reset to initial value output controlled by other pin-shared function output inverts when tnapol is high ccrb ccrp int. flag tnpf tpnb pin (tnboc=1) tpnb pin (tnboc=0) duty cycle set by ccra duty cycle set by ccrb pwm period set by ccrp duty cycle set by ccra duty cycle set by ccra etm pwm mode -- edge aligned note: 1. here tncclr=0 therefore ccrp clears counter and determines the pwm period 2. the internal pwm function continues running even when tnaio [1:0] (or tnbio [1:0]) = 00 or 01 3. ccra controls the tpna pwm duty and ccrb controls the tpnb pwm duty rev. 1.00 98 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver counter value ccra tnon tnpau tnbpol ccrb int. flag tnbf time counter cleared by ccra pause resume stop counter restart tncclr = 1; tnbm [1:0] = 10; tnpwm [1:0] = 00 output pin reset to initial value output controlled by other pin-shared function output inverts when tnbpol is high ccrb ccrp int. flag tnpf tpnb pin (tnboc=1) tpnb pin (tnboc=0) duty cycle set by ccrb pwm period set by ccra etm pwm mode -- edge aligned note: 1. here tncclr=1 therefore ccra clears the counter and determines the pwm period 2. the internal pwm function continues running even when tnbio [1:0] = 00 or 01 3. the ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 4. here the tm pin control register should not enable the tpna pin as a tm output pin. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 99 february 1, 2011 counter value ccrp ccra tnon tnpau tnapol ccra int. flag tnaf ccrb int. flag tnbf tpna pin (tnaoc=1) time pause resume stop counter restart tncclr = 0; tnam [1:0] = 10, tnbm [1:0] = 10; tnpwm [1:0] = 11 output pin reset to initial value output controlled by other pin-shared function output inverts when tnapol is high ccrb ccrp int. flag tnpf tpnb pin (tnboc=1) tpnb pin (tnboc=0) duty cycle set by ccra duty cycle set by ccrb pwm period set by ccrp etm pwm mode -- centre aligned note: 1. here tncclr=0 therefore ccrp clears the counter and determines the pwm period 2. tnpwm [1:0] =11 therefore the pwm is centre aligned 3. the internal pwm function continues running even when tnaio [1:0] (or tnbio [1:0]) = 00 or 01 4. ccra controls the tpna pwm duty and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value rev. 1.00 100 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver counter value ccrp ccra tnon tnpau tnapol ccra int. flag tnaf ccrb int. flag tnbf tpna pin (tnaoc=1) time pause resume stop counter restart tncclr = 0; tnam [1:0] = 10, tnbm [1:0] = 10; tnpwm [1:0] = 11 output pin reset to initial value output controlled by other pin-shared function output inverts when tnapol is high ccrb ccrp int. flag tnpf tpnb pin (tnboc=1) tpnb pin (tnboc=0) duty cycle set by ccra duty cycle set by ccrb pwm period set by ccrp etm pwm mode -- centre aligned note: 1. here tncclr=1 therefore ccra clears the counter and determines the pwm period 2. tnpwm [1:0] =11 therefore the pwm is centre aligned 3. the internal pwm function continues running even when tnbio [1:0] = 00 or 01 4. ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value single pulse output mode to select this mode, the required bit pairs, tnam1, tnam0 and tnbm1, tnbm0 should be set to 10 respectively and also the corresponding tnaio1, tnaio0 and tnbio1, tnbio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse tpna output leading edge is a low to high transition of the tnon bit, which can be implemented using the application program. the trigger for the pulse tpnb output leading edge is a compare match from comparator b, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output of tpna. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge of tpna will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge of tpna and tpnb will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge of tpna and tpnb. in this way the ccra value can be used to control the pulse width of tpna. the ccra-ccrb value can be used to control the pulse width of tpnb. a compare match from comparator a and comparator b will also generate tm interrupts. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr bit is also not used. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 101 february 1, 2011 single pulse generation rev. 1.00 102 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver counter value ccrb ccra tnon tnpau tnapol ccrb int. flag tnbf ccra int. flag tnaf tpna pin (tnaoc=1) time counter stopped by ccra pause resume counter stops by software counter reset when tnon returns high tnam [1:0] = 10, tnbm [1:0] = 10; tnaio [1:0] = 11, tnbio [1:0] = 11 pulse width set by (ccra-ccrb) output inverts when tnbpol=1 tckn pin software trigger cleared by ccra match tckn pin trigger auto. set by tckn pin software trigger software clear software trigger software trigger tnbpol tpna pin (tnaoc=0) tpnb pin (tnboc=1) tpnb pin (tnboc=0) pulse width set by ccra output inverts when tnapol=1 etm -- single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high 5. in the single pulse mode, tnaio [1:0] and tnbio [1:0] must be set to 11 and can not be changed. capture input mode to select this mode bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1 and tmnc2 registers should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tpna and tpnb_0, tpnb_1, tpnb_2 pins, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnaio1, tnaio0 and tnbio1, tnbio0 bits in the tmnc1 and tmnc2 registers. the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpna and tpnb_0, tpnb_1, tpnb_2 pins the present value in the counter will be latched into the ccra and ccrb registers and a tm interrupt generated. irrespective of what events occur on the tpna and tpnb_0, tpnb_1, tpnb_2 pins the counter will continue to free run until the tnon bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tm interrupt will also be generated. counting the number of overflow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the tnaio1, tnaio0 and tnbio1, tnbio0 bits can select the active trigger edge on the tpna and tpnb_0, tpnb_1, tpnb_2 pins to be a rising edge, falling edge or both edge types. if the tnaio1, tnaio0 and tnbio1, tnbio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpna and tpnb_0, tpnb_1, tpnb_2 pins, however it must be noted that the counter will continue to run. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 103 february 1, 2011 counter value yy ccrp tnon tnpau ccrp int. flag tnpf ccra int. flag tnaf ccra value time counter cleared by ccrp pause resume counter reset tnam [1:0] = 01 tm capture pin tpna xx counter stop tnaio [1:0] value xx yy xx yy active edge active edge active edge 00 rising edge 01 falling edge 10 both edges 11 disable capture etm ccra capture input mode note: 1. tnam [1:0] = 01 and active edge set by the tnaio [1:0] bits 2. the tm capture input pin active edge transfers he counter value to ccra 3. tncclr bit not used 4. no output function -- tnaoc and tnapol bits not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero. as the tpna and tpnb_0, tpnb_1, tpnb_2 pins are pin shared with other functions, care must be taken if the tm is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr, tnaoc, tnboc, tnapol and tnbpol bits are not used in this mode. rev. 1.00 104 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver ccrp counter overflow ccrp int. flag tnpf ccrb int. flag tnbf tnon bit pa use counter reset tnpau bit resume sto p yy xx ccrb value xx tm capture pin yy tnbio1, tnbio0 value 00 - rising edge 01 - falling edge 11 - disable capture active edge active edge xx 10 - both edges active edges yy tnbm1, tnbm0 = 01 tim e counter value etm ccrb capture input mode note: 1. tnbm [1:0] = 01 and active edge set by the tnbio [1:0] bits 2. the tm capture input pin active edge transfers the counter value to ccrb 3. tncclr bit not used 4. no output function -- tnboc and tnbpol bits not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero. touch key function each device provides multiple touch key functions. the touch key function is fully integrated and requires no external components, allowing touch key functions to be implemented by the simple manipulation of internal registers. touch key structure the touch keys are pin shared with the pc and pd logic i/o pins, as well as having dedicated pins. for the pin shared touch keys, the touch key function is chosen using register bits. keys are organised into groups of four, with each group known as a module and having a module number, m0 to m4. each module contains its own control logic circuits and register set. examination of the register names will reveal the module number it is referring to. device keys - n touch key module touch key shared i/o pin bs85b12-3 12 m0 k1~k4 pc0~pc3 m1 k5~k8 pc4~pc7 m2 k9~k12 dedicated pins BS85C20-3 20 m0 k1~k4 pc0~pc3 m1 k5~k8 pc4~pc7 m2 k9~k12 dedicated pins m3 k13~k16 pd0~pd3 m4 k17~k20 pd4~pd7 touch key module/pin reference table touch key register definition each touch key module, which contains four touch key functions, has its own suite of registers. the following table shows the register set for each touch key module. the mn within the register name refers to the touch key module number and has a range of m0 to m4. name usage tkmn16dh 16-bit c/f counter high byte tkmn16dl 16-bit c/f counter low byte tkmnc0 control register 0 key select tkmnc1 control register 1 internal reference. touch pad reference. tkmnc2 control register 2 counter on-off and clear control/reference clock control/tkst start bit tkmnc3 control register 3 counter overflow bits register listing bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 105 february 1, 2011 register name bit 76543 2 1 0 tkmn16dh d7 d6 d5 d4 d3 d2 d1 d0 tkmn16dl d7 d6 d5 d4 d3 d2 d1 d0 tkmnc0 mnmxs1 mnmxs0 d5 d4 d3 d2 d1 d0 tkmnc1 mnk4oen mnk3oen mnk2oen mnk1oen mnk4io mnk3io mnk2io mnk1io tkmnc2 mn16cton d6 mnst mnroen mnrcclr mn16ctclr d1 mnros tkmnc3 d9 d8 mnrcov mn16ctov d3 mnrovs2 mnrovs1 mnrovs0 register content summary tkmn16dh register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/wrrrrrrrr p o r00000000 bit 7~0 module n 16-bit counter high byte contents tkmn16dl register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/wrrrrrrrr p o r00000000 bit 7~0 module n 16-bit counter low byte contents tkmnc0 register b i t76543210 name mnmxs1 mnmxs0 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bits 7~6 mnmxs1, mnmxs0 : multiplexer key select bit module number mnmxs1 mnmxs0 m0 m1 m2 m3 m4 0 0 key 1 key 5 key 9 key 13 key 17 0 1 key 2 key 6 key 10 key 14 key 18 1 0 key 3 key 7 key 11 key 15 key 19 1 1 key 4 key 8 key 12 key 16 key 20 bit 5~0 d5~d0 : these bits must be set to the binary value 011000 rev. 1.00 106 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver tkmnc1 register b i t76543210 name mnk4oen mnk3oen mnk2oen mnk1oen mnk4io mnk3io mnk2io mnk1io r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 for the bs85b12-3 n=0~2 while for the BS85C20-3 n=0~4. bits 7~4 mnk4oen~ mnk1oen: key selector control mnk4oen m0 m1 m2 m3 m4 key 4 key 8 key 12 key 16 key 20 0 disable 1 enable mnk3oen m0 m1 m2 m3 m4 key 3 key 7 key 11 key 15 key 19 0 disable 1 enable mnk2oen m0 m1 m2 m3 m4 key 2 key 6 key 10 key 14 key 18 0 disable 1 enable mnk1oen m0 m1 m2 m3 m4 key 1 key 5 key 9 key 13 key 17 0 disable 1 enable bits 3~0 i/o pin or touch key function select mnk4io m0 m1 m3 m4 pc3/key 4 pc7/key 8 pd3/key 16 pd7/key 20 0 i/o pin 1 touch key mnk3io m0 m1 m3 m4 pc2/key 3 pc6/key 7 pd2/key 15 pd6/key 19 0 i/o pin 1 touch key mnk2io m0 m1 m3 m4 pc1/key 2 pc5/key 6 pd1/key 14 pd5/key 18 0 i/o pin 1 touch key mnk1io m0 m1 m3 m4 pc0/key 1 pc4/key 5 pd0/key 13 pd4/key 17 0 i/o pin 1 touch key bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 107 february 1, 2011 tkmnc2 register bit7654 3 210 name mn16cton d6 mnst mnroen mnrcclr mn16ctclr d1 mnros r/w r/w r/w r/w r/w r/w r/w r/w r/w por0000 0 000 bit 7 mn16cton : 16-bit c/f counter control 0: disable 1: enable bit 6 d6 : this bit must be cleared to zero. bit 5 mnst : time slot counter start control 0: time slot counter stopped 0 1: enable time slot counter. when this bit changes from low to high the time slot counter will be enabled and the touch sense procedure started. when the time slot counter has completed its counting an interrupt will be generated. bit 4 mnroen : reference clock control 0: disable 1: enable bit 3 mnrcclr : time slot counter clear control 0: no change 1: clear counter this bit must be first set to 1 and then to 0. bit 2 mn16ctclr : 16-bit c/f counter clear control 0: no change 1: clear counter this bit must be first set to 1 and then to 0. bit 1 d1 : this bit must be cleared to zero. bit 0 mnros : time slot counter clock source 0: reference clock 1: sense key oscillator m0:k4, m1:k8, m2:k12, m3:k16, m4:k20 tkmnc3 register b i t76543210 name d7 d6 mnrcov mn16ctov d3 mnrovs2 mnrovs1 mnrovs0 r/w r r r r/w r/w r/w r/w r/w por0000000 0 bit 7~6 d7, d6 : read only bits -- unknown values bit 5 mnrcov : time slot counter overflow flag 0: no overflow 1: overflow bit 4 mn16ctov : 16-bit c/f counter overflow flag 0: no overflow 1: overflow bit 3 d3 : this bit must be cleared to zero. bit 2~0 mnrovs2~mnrovs0 : time slot counter overflow time setup 000: 64 count 001: 128 count 010: 256 count 011: 512 count 100: 1024 count 101: 2048 count 110: 4096 count 111: 8192 count rev. 1.00 108 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver touch key operation when a finger touches or is in proximity to a touch pad, the capacitance of the pad will increase. by using this capacitance variation to change slightly the frequency of the internal sense oscillator, touch actions can be sensed by measuring these frequency changes. using an internal programmable divider the reference clock is used to generated a fixed time period. by counting the number of generated clock cycles from the sense oscillator during this fixed time period touch key actions can be determined. each touch key module contains four touch key inputs which are either dedicated touch key pins or are shared logical i/o pins. if shared, the desired function is selected using register bits. each touch key has its own independent sense oscillator. there are therefore four sense oscillators within each touch key module. each touch key module also has its own interrupt vector and set of interrupts flags. during this reference clock fixed interval, the number of clock cycles generated by the sense oscillator is measured, and it is this value that is used to determine if a touch action has been made or not. at the end of the fixed reference clock time interval, a touch key interrupt signal will be generated. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 109 february 1, 2011 c/f & mux. mux. reference clock touch key (1 set = touch key*5) key0 key1 key2 key3 16-bit c/f counter 16-bit c/f counter overflow flag 16-bit c/f counter int flag time slot counter time slot counter overflow flag time slot counter int flag enable time slot counter clock select touch switch module block diagram % 4 " 7 4 $ ) $ ! ) $ ) $ ) = - % / % 4 " 7 4 = - % / % 4 " 7 4 = - % / % 4 " 7 4 = - % / touch key or i/o function select touch key interrupt each touch key module, which consists of four touch keys, has two independent interrupts, one for each of the, 16-bit c/f counter and time slot counter. the time slot counter interrupt has its own interrupt vector while the 16-bit c/f counter interrupts are contained within the multi-function interrupts and therefore do not have their own vector. care must be taken during programming as the 16-bit c/f counter interrupt flags contained within the multi-function interrupts will not be automatically reset upon entry into the interrupt service routine but rather must be reset manually by the application program. more details regarding the touch key interrupts are located in the interrupt section of the datasheet. programming considerations after the relevant registers are setup, the touch key detection process is initiated the changing the mnst bit from low to high. this will enable and synchronise all relevant oscillators. the mnrcov flag, which is the time slot counter flag will go high and remain high until the counter overflows. when this happens an interrupt signal will be generated. when the external touch key size and layout are defined, their related capacitances will then determine the sensor oscillator frequency. rev. 1.00 110 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver serial interface module sim these devices contain a serial interface module, which includes both the four line spi interface or the two line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory, etc. the sim pins are pin shared with other i/o pins and must be selected using the simen bit in the simc0 register. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 register. spi interface the spi interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either master or slave. although the spi interface specification can control multiple slave devices from a single master, but this device provided only one scs pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pin to select the slave devices. spi interface operation the spi interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin-shared with normal i/o pins and with the i 2 c function pins, the spi interface must first be enabled by setting the correct bits in the simc0 and simc2 registers. communication between devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. the master also controls the clock signal. as the device only contains a single scs pin only one slave device can be utilized. the scs pin is controlled by software, set csen bit to 1 to enable scs pin function, set csen bit to 0 the scs pin will be as i/o function. the spi function in this device offers the following features: full duplex synchronous data transfer both master and slave modes lsb first or msb first data transmission modes transmission complete flag rising or falling active clock edge the status of the spi interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen and simen. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 111 february 1, 2011 1 1 1 1 1 1 1 1 1 1 spi master/slave connection spi registers there are three internal registers which control the overall operation of the spi interface. these are the simd data register and two registers simc0 and simc2. note that the simc1 register is only used by the i 2 c interface. register name bit 76543210 simc0 sim2 sim1 sim0 pcken pckp1 pckp0 simen simd d7 d6 d5 d4 d3 d2 d1 d0 simc2 d7 d6 ckpolb ckeg mls csen wcol trf spi register list the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the spi bus, the de- vice can read it from the simd register. any transmission or reception of data from the spi bus must be made via the simd register. simd register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o rxxxxxxxx x unknown rev. 1.00 112 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver 4 1 1 1 $ = = 1 % 0 7 4 4 / 1 4 - 7 8 " - 7 - > 6 7 - / - - > 1 1 - 0 1 2 1 0 " 1 1 ' ) 1 1 ' ) " ) spi block diagram there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi function, only by the i 2 c function. register simc0 is used to control the enable/disable function and to set the data transmission clock frequency. although not connected with the spi function, the simc0 register is also used to control the peripheral clock prescaler. register simc2 is used for other control functions such as lsb/msb selection, write collision flag etc. simc0 register b i t76543210 name sim2 sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w p o r1110000 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f lirc 100: unused 101: spi slave mode 110: i 2 c slave mode 111: unused these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen : sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared, the sdi, sdo, sck and scs , or sda and scl lines will be as i/o function and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. if the sim is configured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be first initialised by the application program. if the sim is configured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as 0 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 113 february 1, 2011 simc2 register b i t76543210 name d7 d6 ckpolb ckeg mls csen wcol trf r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7~6 undefined bit this bit can be read or written by user software program. bit 5 ckpolb : determines the base condition of the clock line 0: the sck line will be high when the clock is inactive 1: the sck line will be low when the clock is inactive the ckpolb bit determines the base condition of the clock line, if the bit is high, then the sck line will be low when the clock is inactive. when the ckpolb bit is low, then the sck line will be high when the clock is inactive. bit 4 ckeg : determines spi sck active clock edge type ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. the ckpolb bit determines the base condition of the clock line, if the bit is high, then the sck line will be low when the clock is inactive. when the ckpolb bit is low, then the sck line will be high when the clock is inactive. the ckeg bit determines active clock edge type which depends upon the condition of ckpolb bit. bit 3 mls : spi data shift order 0: lsb 1: msb this is the data shift select bit and is used to select how the data is transferred, either msb or lsb first. setting the bit high will select msb first and low for lsb first. bit 2 csen : spi scs pin control 0: disable 1: enable the csen bit is used as an enable/disable for the scs pin. if this bit is low, then the scs pin will be disabled and as i/o function. if the bit is high the scs pin will be enabled and used as a select pin. bit 1 wcol : spi write collision flag 0: no collision 1: collision the wcol flag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simd register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. bit 0 trf : spi transmit/receive complete flag 0: data is being transferred 1: spi data transmission is completed the trf bit is the transmit/receive complete flag and is set 1 automatically when an spi data transmission is completed, but must set to 0 by the application program. it can be used to generate an interrupt. rev. 1.00 114 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver spi communication after the spi interface is enabled by setting the simen bit high, then in the master mode, when data is written to the simd register, transmission/reception will begin simultaneously. when the data transfer is complete, the trf flag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd register. the master should output an scs signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs signal depending upon the configurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various configurations of the ckpolb and ckeg bits. the spi will continue to function even in the idle mode. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 115 february 1, 2011 1 ? " : @ 1 ? " : @ 1 1 1 1 * ! ! * 8 1 $ ? 1 6 4 % 7 - 0 4 1 6 7 @ spi slave mode timing ckeg=0 1 ? " : . a : @ 1 $ ' . 1 ' : 1 $ ' : . 1 ' : ? = - - - , 3 7 % @ 1 ? " : . a : @ 1 ? " : . a : @ 1 ? " : . a : @ 1 ? a : @ 1 ? a : @ 1 1 1 * ! ! * * ! ! * 8 1 $ spi master mode timing rev. 1.00 116 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver 1 $ ' : 8 1 $ 8 " : b - 8 " 2 4 # 4 4 # - 6 b ? : b @ ' 2 6 0 # 1 $ - 4 0 4 % 6 b ' 2 ' # 4 4 - 5 b $ 4 1 - 5 1 4 0 0 7 " . a . 1 ' 6 $ " 1 1 $ c d e : . . . 1 $ c d e : ' spi transfer control flowchart 1 ? " : @ 1 ? " : @ 1 1 1 1 * ! ! * 8 1 $ ? 1 % 7 4 4 4 4 < 7 4 f 1 4 0 - 7 0 1 1 : @ ' d 1 4 - 5 # 6 . 0 1 $ ' : 6 1 ' : . 1 4 - < / 4 ) - 6 6 7 4 % 1 1 - 5 - g spi slave mode timing ckeg=1 i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom memory etc. originally developed by philips, it is a two line low speed serial interface for synchronous serial data transfer. the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c interface operation the i 2 c serial interface is a two line interface, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identified by a unique address which will be transmitted and received on the i 2 c bus. when two devices communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the slave device. both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. for these devices, which only operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 117 february 1, 2011 5 1 - 5 5 $ 4 5 1 - 5 ; 1 1 " i 2 c master slave bus connection 7 4 ? 1 $ @ 1 - 5 6 6 4 4 7 4 ? 1 $ @ 1 % 0 7 4 - $ ( h 6 6 4 4 $ % 3 1 " 1 $ 1 4 # 5 - ( i , ) # - 1 1 4 6 6 4 4 # ) - 4 ) - > < - 6 7 6 < 1 - 5 1 8 3 3 h 1 " 1 3 i 2 c block diagram the debounce time, if selected, can be chosen to be either 1 or 2 system clocks. i 2 c registers there are four control registers associated with the i 2 c bus, simc0, simc1, sima and i2ctoc and one data register, simd. the simd register, which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the i 2 c bus, the microcontroller can read it from the simd register. any transmission or reception of data from the i 2 c bus must be made via the simd register. the sim pins are pin shared with other i/o pins and must be selected using the simen bit in the simc0 register. note that the sima register also has the name simc2 which is used by the spi function. bit simen and bits sim2~sim0 in register simc0 are used by the i 2 c interface. register name bit 76543210 simc0 sim2 sim1 sim0 pcken pckp1 pckp0 simen simc1 hcf haas hbb htx txak srw iamwu rxak simd d7 d6 d5 d4 d3 d2 d1 d0 sima iica6 iica5 iica4 iica3 iica2 iica1 iica0 d0 i2ctoc i2ctoen i2ctof i2ctos5 i2ctos4 i2ctos3 i2ctos2 i2ctos1 i2ctos0 i 2 c register list rev. 1.00 118 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver 1 4 7 - 0 # $ 4 1 6 4 - 5 6 6 4 4 6 8 ) 0 # $ 4 > < - 6 7 0 # 4 - 5 1 6 6 ) / 0 # $ 4 > < - 6 7 0 # 4 - 5 1 4 7 - 0 # $ 4 simc0 register b i t76543210 name sim2 sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w p o r1110000 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f lirc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control described elsewhere bit 3~2 pckp1, pckp0 : select pck output pin frequency described elsewhere bit 1 simen : sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared, the sdi, sdo, sck and scs , or sda and scl lines will be as i/o function and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. if the sim is configured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be first initialised by the application program. if the sim is configured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as 0 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 119 february 1, 2011 simc1 register b i t76543210 name hcf haas hbb htx txak srw iamwu rxak r/w r r r r/w r/w r r/w r p o r10000001 bit 7 hcf:i 2 c bus data transfer completion flag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 haas:i 2 c bus address match flag 0: not address match 1: address match the hass flag is the address match flag. this flag is used to determine if the slave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the flag will be low. bit 5 hbb:i 2 c bus busy flag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbb flag is the i 2 c busy flag. this flag will be 1 when the i 2 c bus is busy which will occur when a start signal is detected. the flag will be set to 0 when the bus is free which will occur when a stop signal is detected. bit 4 htx : select i 2 c slave device is transmitter or receiver 0: slave device is the receiver 1: slave device is the transmitter bit 3 txak:i 2 c bus transmit acknowledge flag 0: slave send acknowledge flag 1: slave do not send acknowledge flag the txak bit is the transmit acknowledge flag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set txak bit to 0 before further data is received. bit 2 srw :i 2 c slave read/write flag 0: slave device should be in receive mode 1: slave device should be in transmit mode the srw flag is the i 2 c slave read/write flag. this flag determines whether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the haas flag is set high, the slave device will check the srw flag to determine whether it should be in transmit mode or receive mode. if the srw flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the srw flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 iamwu:i 2 c address match wake-up control 0: disable 1: enable this bit should be set to 1 to enable i 2 c address match wake-up from sleep or idle mode. bit 0 rxak:i 2 c bus receive acknowledge flag 0: slave receive acknowledge flag 1: slave do not receive acknowledge flag the rxak flag is the receiver acknowledge flag. when the rxak flag is 0 , it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak flag to determine if the master receiver wishes to receive the next byte. the slave transmitter will therefore continue sending out data until the rxak flag is 1 . when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. rev. 1.00 120 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver i2ctoc register b i t76543210 name i2ctoen i2ctof i2ctos5 i2ctos4 i2ctos3 i2ctos2 i2ctos1 i2ctos0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7 i2ctoen :i 2 c time-out control 0: disable 1: enable bit 6 i2ctof : time-out flag 0: no time-out 1: time-out occurred bit 5~0 i2ctos5 ~ i2ctos0 : time-out time definition i 2 c time-out clock source is f lirc /32. i 2 c time-out time is given by: [i2ctos5 : i2ctos0]+1) x (32/f lirc ) the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the i 2 c bus, the de - vice can read it from the simd register. any transmission or reception of data from the i 2 c bus must be made via the simd register. simd register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o rxxxxxxxx x unknown sima register b i t76543210 name iica6 iica5 iica4 iica3 iica2 iica1 iica0 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o rxxxxxxxx x unknown bit 7~1 iica6~ iica0 :i 2 c slave address iica6~ iica0 is the i 2 c slave address bit 6~bit 0. the sima register is also used by the spi interface but has the name simc2. the sima register is the location where the 7-bit slave address of the slave device is stored. bits 7~1 of the sima register define the device slave address. bit 0 is not defined. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register, the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. bit 0 undefined bit this bit can be read or written by user software program. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 121 february 1, 2011 i 2 c bus communication communication on the i 2 c bus requires four separate steps, a start signal, a slave device address transmission, a data transmission and finally a stop signal. when a start signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. the first seven bits of the data will be the slave address with the first bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must first check the condition of the haas bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. during a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the srw bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus, the following are steps to achieve this: step 1 set the sim2~sim0 and simen bits in the simc0 register to 1 to enable the i 2 c bus. step 2 write the slave address of the device to the i 2 c bus address register sima. step 3 set the sime and sim muti-function interrupt enable bit of the interrupt control register to enable the sim interrupt and multi-function interrupt. i 2 c bus start signal the start signal can only be generated by the master device connected to the i 2 c bus and not by the slave device. this start signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a start condition occurs when a high to low transition on the sda line takes place when the scl line remains high. rev. 1.00 122 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver 1 8 1 - 5 6 6 4 4 1 $ 1 1 $ c d e : 1 1 $ ' 4 : b 2 4 ' 1 1 8 0 a $ 7 # - 1 - - 1 6 6 < % 7 4 1 a $ 7 # i 2 c bus initialisation flow chart slave address the transmission of a start signal by the master will be detected by all devices on the i 2 c bus. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the start signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the master matches the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal will be generated. the next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the srw bit of the simc1 register. the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status flag haas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, the haas bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c bus read/write signal the srw bit in the simc1 register defines whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver. if the srw flag is 1 then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter. if the srw flag is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 123 february 1, 2011 1 : 1 ? ) @ 1 : 1 - 5 6 6 4 4 ? * ) 4 @ 1 : 1 8 ) ? ) @ $ : 1 - 5 6 5 4 6 > < - 6 7 ) ? ) @ : ? i ) 4 @ : ? h ) 0 4 # . h ) 0 5 ) @ : 1 ? ) @ 1 " 1 1 1 8 1 1 " 1 1 - 5 6 6 4 4 1 1 1 $ 1 1 1 $ note: * when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c communication timing diagram i 2 c bus slave address acknowledge signal after the master has transmitted a calling address, any slave device on the i 2 c bus, whose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a stop signal must be transmitted by the master to end the communication. when the haas flag is high, the addresses have matched and the slave device must check the srw flag to determine if it is to be a transmitter or a receiver. if the srw flag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to 1 . if the srw flag is low, then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be set to 0 . i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb first and the lsb last. after receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level 0 , before it can receive the next data byte. if the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the corresponding data will be stored in the simd register. if setup as a transmitter, the slave device must first write the data to be transmitted into the simd register. if setup as a receiver, the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the slave device, which is setup as a transmitter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master. rev. 1.00 124 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver 1 3 1 : b 3 h : b 1 8 : b 2 4 ' 2 4 ' h : b 2 4 ' ' 6 0 # 1 $ - 4 1 " - 2 4 # # / 6 0 # 1 $ - 4 1 " " 8 6 1 $ - 4 1 " " 1 3 h 8 6 1 $ - 4 1 " " " 3 h " h # # / 6 0 # 1 $ - 4 1 " " " 3 h " h i 2 c bus isr flow chart i 2 c time-out control in order to reduce the problem of i 2 c lockup due to reception of erroneous clock sources, clock, a time-out function is provided. if the clock source to the i 2 c is not received then after a fixed time period, the i 2 c circuitry and registers will be reset. the time-out counter starts counting on an i 2 c bus start & address match condition, and is cleared by an scl falling edge. before the next scl falling edge arrives, if the time elapsed is greater than the time-out setup by the i2ctoc register, then a time-out condition will occur. the time-out function will stop when an i 2 c stop condition occurs. when an i 2 c time-out counter overflow occurs, the counter will stop and the i2ctoen bit will be cleared to zero and the i2ctf bit will be set high to indicate that a time-out condition as occurred. the time-out condition will also generate an interrupt which uses the i 2 c interrrupt vector. when an i 2 c time-out occurs the i 2 c internal circuitry will be reset and the registers will be reset into the following condition: register after i 2 c time-out simdr, simar, simc0 no change simc1 reset to por condition i 2 c registers after time-out the i2ctof flag can be cleared by the application program. there are 64 time-out periods which can be selected using bits in the i2ctoc register. the time-out time is given by the formula: ((1~64) 32)/f lirc . this gives a range of about 1ms to 64ms. note also that the lirc oscillator is continuously enabled. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 125 february 1, 2011 # , 4 # , 4 1 " 7 5 4 1 " 1 1 1 8 1 1 " 1 1 - 5 6 6 4 4 i 2 c time-out peripheral clock output the peripheral clock output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. peripheral clock operation as the peripheral clock output pin, pck, is shared with i/o line, the required pin function is chosen via pcken in the simc0 register. the peripheral clock function is controlled using the simc0 register. the clock source for the peripheral clock output can originate from either the tm0 ccrp match frequency/2 or a divided ratio of the internal f sys clock. the pcken bit in the simc0 register is the overall on/off control, setting pcken bit to 1 enables the peripheral clock, setting pcken bit to 0 disables it. the required division ratio of the system clock is selected using the pckp1 and pckp0 bits in the same register. if the device enters the sleep mode this will disable the peripheral clock output. simc0 register b i t76543210 name sim2 sim1 sim0 pcken pckpsc1 pckpsc0 simen r/w r/w r/w r/w r/w r/w r/w r/w p o r1110000 bit 7~5 sim2~sim0 : sim operating mode control described elsewhere bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckpsc1, pckpsc0 : select pck output pin frequency 0: f sys 1: f sys /4 2: f sys /8 3: tm0 ccrp match frequency/2 bit 1 simen : sim control described elsewhere bit 0 unimplemented, read as 0 rev. 1.00 126 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a touch action or timer module requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the devices contains several external interrupt and internal interrupts functions. the external interrupt is generated by the action of the external int pin, while the internal interrupts are generated by various internal functions such as the touch keys, timer module, time base, sim etc. interrupt registers overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the special purpose data memory, as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. the first is the intc0~intc3 registers which setup the primary interrupts, the second is the mfi0~mfi5 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specific pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request flag. function enable bit request flag notes global emi int pin intne intnf n=0 or 1 touch key module tkmne tkmnf n=0~4 sim sim sif eeprom dee def multi-function mfne mfnf n=0~5 time base tbne tbnf n=0 or 1 lvd lvf lve external peripheral xpe xpf tm tnpe tnpf n=0~2 tnae tnaf n=0~2 tnbe tnbf n=0~2 interrupt register bit naming conventions bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 127 february 1, 2011 interrupt register contents bs85b12-3 name bit 76543210 integ int1s1 int1s0 int0s1 int0s0 intc0 simf int1f int0f sime int1e int0e emi intc1 tb0f tkm2f tkm1f tkm0f tb0e tkm2e tkm1e tkm0e intc2 mf3f mf2f mf1f mf0f mf3e mf2e mf1e mf0e mfi0 m116ctf d6 m016ctf d4 m116cte d2 m016cte d0 mfi1 t0af t0pf m216ctf d4 t0ae t0pe m216cte d0 mfi2 t1bf t1af t1pf t1be t1ae t1pe mfi3 def lvf xpf tb1f dee lve xpe tb1e BS85C20-3 name bit 76543210 integ int1s1 int1s0 int0s1 int0s0 intc0 simf int1f int0f sime int1e int0e emi intc1 tb0f tkm2f tkm1f tkm0f tb0e tkm2e tkm1e tkm0e intc2 mf3f mf2f mf1f mf0f mf3e mf2e mf1e mf0e intc3 mf5f mf4f tkm4f tkm3f mf5e mf4e tkm4e tkm3e mfi0 m116ctf d6 m016ctf d4 m116cte d2 m016cte d0 mfi1 t0af t0pf m216ctf d4 t0ae t0pe m216cte d0 mfi2 t1bf t1af t1pf t1be t1ae t1pe mfi3 def lvf xpf tb1f dee lve xpe tb1e mfi4 m416ctf d6 m316ctf d4 m416cte d2 m316cte d0 mfi5 t2af t2pf t2ae t2pe rev. 1.00 128 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver integ register all devices b i t76543210 name int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0000 bit 7~2 unimplemented, read as 0 bit 1~0 int1s1, int1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1, int0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges intc0 register all devices b i t76543210 name simf int1f int0f sime int1e int0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0000000 bit 7 unimplemented, read as 0 bit 6 simf : sim interrupt request flag 0: no request 1: interrupt request bit 5 int1f : int1 pin interrupt request flag 0: no request 1: interrupt request bit 4 int0f : int0 pin interrupt request flag 0: no request 1: interrupt request bit 3 sime : sim interrupt control 0: disable 1: enable bit 2 int1e : int1 pin interrupt control 0: disable 1: enable bit 1 int0e : int0 pin interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 129 february 1, 2011 intc1 register all devices b i t76543210 name tb0f tkm2f tkm1f tkm0f tb0e tkm2e tkm1e tkm0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 tb0f : time base 0 interrupt request flag 0: no request 1: interrupt request bit 6 tkm2f : touch key module 2 interrupt request flag 0: no request 1: interrupt request bit 5 tkm1f : touch key module 1 interrupt request flag 0: no request 1: interrupt request bit 4 tkm0f : touch key module 0 interrupt request flag 0: no request 1: interrupt request bit 3 tb0e : time base 0 interrupt control 0: disable 1: enable bit 2 tkm2e : touch key module 2 interrupt control 0: disable 1: enable bit 1 tkm1e : touch key module 1 interrupt control 0: disable 1: enable bit 0 tkm0e : touch key module 0 interrupt control 0: disable 1: enable intc2 register all devices b i t76543210 name mf3f mf2f mf1f mf0f mf3e mf2e mf1e mf0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 mf3f : multi-function interrupt 3 request flag 0: no request 1: interrupt request bit 6 mf2f : multi-function interrupt 2 request flag 0: no request 1: interrupt request bit 5 mf1f : multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 4 mf0f : multi-function interrupt 0 request flag 0: no request 1: interrupt request bit 3 mf3e : multi-function interrupt 3 control 0: disable 1: enable bit 2 mf2e : multi-function interrupt 2 control 0: disable 1: enable bit 1 mf1e : multi-function interrupt 1 control 0: disable 1: enable bit 0 mf0e : multi-function interrupt 0 control 0: disable 1: enable rev. 1.00 130 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver intc3 register bs85c20 only b i t76543210 name mf5f mf4f tkm4f tkm3f mf5e mf4e tkm4e tkm3e r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 mf5f : multi-function interrupt 5 request flag 0: no request 1: interrupt request bit 6 mf4f : multi-function interrupt 4 request flag 0: no request 1: interrupt request bit 5 tkm4f : touch key module 4 interrupt request flag 0: no request 1: interrupt request bit 4 tkm3f : touch key module 3 interrupt request flag 0: no request 1: interrupt request bit 3 mf5e : multi-function interrupt 5 control 0: disable 1: enable bit 2 mf4e : multi-function interrupt 4 control 0: disable 1: enable bit 1 tkm4e : touch key module 4 interrupt control 0: disable 1: enable bit 0 tkm3e : touch key module 3 interrupt control 0: disable 1: enable mfi0 register all devices b i t76543210 name m116ctf d6 m016ctf d4 m116cte d2 m016cte d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 m116ctf : touch key module 1 16-bit counter interrupt request flag 0: no request 1: interrupt request bit 6 d6 : this bit must be cleared to zero bit 5 m016ctf : touch key module 0 16-bit counter interrupt request flag 0: no request 1: interrupt request bit 4 d4 : this bit must be cleared to zero bit 3 m116cte : touch key module 1 16-bit timer interrupt control 0: disable 1: enable bit 2 d2 : this bit must be cleared to zero bit 1 m016cte : touch key module 0 16-bit timer interrupt control 0: disable 1: enable bit 0 d0 : this bit must be cleared to zero bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 131 february 1, 2011 mfi1 register all devices b i t76543210 name t0af t0pf m216ctf d4 t0ae t0pe m216cte d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 t0af : tm0 comparator a match interrupt request flag 0: no request 1: interrupt request bit 6 t0pf : tm0 comparator p match interrupt request flag 0: no request 1: interrupt request bit 5 m216ctf : touch key module 2 16-bit counter interrupt request flag 0: no request 1: interrupt request bit 4 d4 : this bit must be cleared to zero bit 3 t0ae : tm0 comparator a match interrupt control 0: disable 1: enable bit 2 t0pe : tm0 comparator p match interrupt control 0: disable 1: enable bit 1 m216cte : touch key module 2 16-bit counter interrupt control 0: disable 1: enable bit 0 d0 : this bit must be cleared to zero mfi2 register all devices b i t76543210 name t1bf t1af t1pf t1be t1ae t1pe r/w r/w r/w r/w r/w r/w r/w por 000 000 bit 7 unimplemented, read as 0 bit 6 t1bf : tm1 comparator b match interrupt request flag 0: no request 1: interrupt request bit 5 t1af : tm1 comparator a match interrupt request flag 0: no request 1: interrupt request bit 4 t1pf : tm1 comparator p match interrupt request flag 0: no request 1: interrupt request bit 3 unimplemented, read as 0 bit 2 t1be : tm1 comparator b match interrupt control 0: disable 1: enable bit 1 t1ae : tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe : tm1 comparator p match interrupt control 0: disable 1: enable rev. 1.00 132 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver mfi3 register all devices b i t76543210 name def lvf xpf tb1f dee lve xpe tb1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 def : data eeprom interrupt request flag 0: no request 1: interrupt request bit 6 lvf : lvd interrupt request flag 0: no request 1: interrupt request bit 5 xpf : external peripheral interrupt request flag 0: no request 1: interrupt request bit 4 tb1f : time base 1 interrupt request flag 0: no request 1: interrupt request bit 3 dee : data eeprom interrupt control 0: disable 1: enable bit 2 lve : lvd interrupt control 0: disable 1: enable bit 1 xpe : external peripheral interrupt control 0: disable 1: enable bit 0 tb1e : time base 1 interrupt control 0: disable 1: enable mfi4 register bs85c20 only b i t76543210 name m416ctf d6 m316ctf d4 m416cte d2 m316cte d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 m416ctf : touch key module 4 16-bit counter interrupt request flag 0: no request 1: interrupt request bit 6 d6 : this bit must be cleared to zero bit 5 m316ctf : touch key module 3 16-bit counter interrupt request flag 0: no request 1: interrupt request bit 4 d4 : this bit must be cleared to zero bit 3 m416cte : touch key module 4 16-bit counter interrupt control 0: disable 1: enable bit 2 d2 : this bit must be cleared to zero bit 1 m316cte : touch key module 3 16-bit counter interrupt control 0: disable 1: enable bit 0 d0 : this bit must be cleared to zero mfi5 register bs85c20 only b i t76543210 name t2af t2pf t2ae t2pe r/w r/w r/w r/w r/w bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 133 february 1, 2011 por 00 00 bit 7~6 unimplemented, read as 0 bit 5 t2af : tm2 comparator a match interrupt request flag 0: no request 1: interrupt request bit 4 t2pf : tm2 comparator p match interrupt request flag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t2ae : tm2 comparator a match interrupt control 0: disable 1: enable bit 0 t2pe : tm2 comparator p match interrupt control 0: disable 1: enable interrupt operation when the conditions for an interrupt event occur, such as a touch key counter overflow, timer module overflow, etc. the relevant interrupt request flag will be set. whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp instruction which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti instruction, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. rev. 1.00 134 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is applied. all of the interrupt request flags when set will wake-up the device if it is in sleep or idle mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device enters the sleep or idle mode. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 135 february 1, 2011 3 i 3 3 3 3 i 3 ; $ 6 4 ) - 6 1 $ = - ' $ $ $ $ 3 3 $ 1 $ 1 $ $ $ = = = = ) - = = j 4 - 7 , , 4 1 j 4 - 7 , , 4 1 $ ' # j 4 - 7 4 ) - 4 $ 4 ) - / 3 7 % ' % / $ 6 - % / $ 6 - $ g $ $ $ $ ' # j 4 - 7 4 ) - 4 i 3 $ 3 $ # 4 % / $ 6 - 1 $ = - ' $ $ $ ' $ g $ g $ $ $ $ $ , ) 5 0 - < $ $ $ , ) 5 0 - < $ $ $ $ $ $ $ $ $ , ) 5 0 - < $ 3 $ $ g ! $ ! $ ! # 4 ' h h " ; " ; " ; $ $ ! $ ! $ ! 3 % / $ 6 - ! $ $ $ ! 3 % / $ 6 - ! i 3 $ $ g $ $ ! 3 $ $ g $ $ $ , ) 5 0 - < $ ! , ) 5 0 - < $ ! $ ! $ $ $ $ " < interrupt structure external interrupt the external interrupt is controlled by signal transitions on the int0 and int1 pins. an external interrupt request will take place when the external interrupt request flag, int0f or int1f, is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e or int1e, must first be set. additionally the correct interrupt edge type must be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pin is pin-shared with i/o pin, it can only be configured as external interrupt pin if the external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. when the interrupt is serviced, the external interrupt request flag, intf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. multi-function interrupt within these devices there are four or six multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from the touch key module, timer module, low voltage detector, eeprom, external peripheral and time base interrupt sources. a multi-function interrupt request will take place when any of the multi-function interrupt request flags, mfnf are set. the multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. to allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi-function request flag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that, although the multi-function interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the multi-function interrupts, namely the touch key module timer interrupts, will not be automatically reset and must be manually reset by the application program. time base interrupts the function of the time base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overflow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. to allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and time base enable bits, tb0e or tb1e, must first be set. when the interrupt is enabled, the stack is not full and the time base overflows, a subroutine call to their respective vector locations will take place. when the interrupt is serviced, the respective interrupt request flag, tb0f or tb1f, will be automatically reset and the emi bit will be cleared to disable other interrupts. rev. 1.00 136 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver the purpose of the time base interrupt is to provide an interrupt signal at fixed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the time base interrupt period, can originate from several different sources, as shown in the system operating mode section. tbc register b i t76543210 name tbon tbck tb11 tb10 d3 tb02 tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00110111 bit 7 tbon : tb0 and tb1 control 0: disable 1: enable bit 6 tbck : select f tb clock 0: f tbc 1: f sys /4 bit 5~4 tb11 ~tb10 : select time base 1 time-out period 0: 4096/f tb 1: 8192/f tb 2: 16384/f tb 3: 32768/f tb bit 3 undefined bit this bit can be read or written by user software program. bit 2~0 tb02~tb00 : select time base 0 time-out period 0: 256/f tb 1: 512/f tb 2: 1024/f tb 3: 2048/f tb 4: 4096/f tb 5: 8192/f tb 6: 16384/f tb 7: 32768/f tb bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 137 february 1, 2011 $ ( h " 0 1 2 1 & i & & # 4 # 4 & 0 0 time base structure external peripheral interrupt the external peripheral interrupt operates in a similar way to the external interrupt and is contained within the multi-function interrupt. a peripheral interrupt request will take place when the external peripheral interrupt request flag, xpf, is set, which occurs when a negative edge transition appears on the pint pin. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, external peripheral interrupt enable bit, xpe, and associated multi-function interrupt enable bit, must first be set. when the interrupt is enabled, the stack is not full and a negative transition appears on the external peripheral interrupt pin, a subroutine call to the respective multi-function interrupt, will take place. when the external peripheral interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request flag will be also automatically cleared. as the xpf flag will not be automatically cleared, it has to be cleared by the application program. the external peripheral interrupt pin is pin-shared with several other pins with different functions. it must therefore be properly configured to enable it to operate as an external peripheral interrupt pin. lvd interrupt the low voltage detector interrupt is contained within the multi-function interrupt. an lvd interrupt request will take place when the lvd interrupt request flag, lvf, is set, which occurs when the low voltage detector function detects a low power supply voltage. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, low voltage interrupt enable bit, lve, and associated multi-function interrupt enable bit, must first be set. when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the multi-function interrupt vector, will take place. when the low voltage interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request flag will be also automatically cleared. as the lvf flag will not be automatically cleared, it has to be cleared by the application program. tm interrupts the compact and standard type tms have two interrupts each, while the enhanced type tm has three interrupts. all of the tm interrupts are contained within the multi-function interrupts. for each of the compact and standard type tms there are two interrupt request flags tnpf and tnaf and two enable bits tnpe and tnae. for the enhanced type tm there are three interrupt request flags tnpf, tnaf and tnbf and three enable bits tnpe, tnae and tnbe. a tm interrupt request will take place when any of the tm request flags are set, a situation which occurs when a tm comparator p, a or b match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must first be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf flag will be automatically cleared. as the tm interrupt request flags will not be automatically cleared, they have to be cleared by the application program. rev. 1.00 138 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver eeprom interrupt the eeprom interrupt, is contained within the multi-function interrupt. an eeprom interrupt request will take place when the eeprom interrupt request flag, def, is set, which occurs when an eeprom write cycle ends. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, eeprom interrupt enable bit, dee, and associated multi-function interrupt enable bit, must first be set. when the interrupt is enabled, the stack is not full and an eeprom write cycle ends, a subroutine call to the respective multi-function interrupt vector, will take place. when the eeprom interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request flag will be also automatically cleared. as the def flag will not be automatically cleared, it has to be cleared by the application program. touch key interrupts for a touch key interrupt to occur, the global interrupt enable bit, emi, and the corresponding touch key interrupt enable tkmne must be first set. an actual touch key interrupt will take place when the touch key request flag. tkmnf, is set, a situation that will occur when the 13-bit time slot counter in the relevant touch key module overflows. when the interrupt is enabled, the stack is not full and the touch key time slot counter overflow occurs, a subroutine call to the relevant touch key interrupt vector, will take place. when the interrupt is serviced, the touch key interrupt request flag, tkmnf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. sim interrupt a sim interrupt request will take place when the sim interrupt request flag, simf, is set, which occurs when a byte of data has been received or transmitted by the sim interface. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, sime, must first be set. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the sim interface, a subroutine call to the respective interrupt vector, will take place. when the serial interface interrupt is serviced, the sim interrupt request flag, sif, will be automatically cleared and the emi bit will be automatically cleared to disable other interrupts. interrupt wake-up function each of the interrupt functions has the capability of waking up the microcontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 139 february 1, 2011 programming considerations by disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. where a certain interrupt is contained within a multi-function interrupt, then when the interrupt service routine is executed, as only the multi-function interrupt request flags, mfnf, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in sleep or idle mode, the wake up being generated when the interrupt request flag changes from low to high. if it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts. low voltage detector lvd each device has a low voltage detector function, also known as lvd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low voltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name lvdc. three bits in this register, vlvd2~vlvd0, are used to select one of eight fixed voltages below which a low voltage condition will be detemined. a low voltage condition is indicated when the lvdo bit is set. if the lvdo bit is low, this indicates that the v dd voltage is above the preset low voltage value. the lvden bit is used to control the overall on/off function of the low voltage detector. setting the bit high will enable the low voltage detector. clearing the bit to zero will switch off the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. rev. 1.00 140 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver lvdc register b i t76543210 name lvdo lvden vlvd2 vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 00 000 bit 7~6 unimplemented, read as 0 bit 5 lvdo : lvd output flag 0: no low voltage detect 1: low voltage detect bit lvden : low voltage detector control 0: disable 1: enable bit 3 unimplemented, read as 0 bit 2~0 vlvd2 ~ vlvd0 : select lvd voltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.2v lvd operation the low voltage detector function operates by comparing the power supply voltage, v dd , with a pre-specified voltage level stored in the lvdc register. this has a range of between 2.0v and 4.2v. when the power supply voltage, v dd , falls below this pre-determined value, the lvdo bit will be set high indicating a low power supply voltage condition. the low voltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the lvden bit is high. after enabling the low voltage detector, a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly, at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. the low voltage detector also has its own interrupt which is contained within one of the multi-function interrupts, providing an alternative means of low voltage detection, in addition to polling the lvdo bit. the interrupt will only be generated after a delay of t lvd after the lvdo bit has been set high by a low voltage condition. when the device is powered down the low voltage detector will remain active if the lvden bit is high. in this case, the lvf interrupt request flag will be set, causing an interrupt to be generated if v dd falls below the preset lvd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low voltage detector wake up function is not required then the lvf flag should be first set high before the device enters the sleep or idle mode. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 141 february 1, 2011 ; ; " ; " ; ' " ; " ; 1 lvd operation lcd driver scom and sseg function the devices can drive lcd panels by simulating lcd signals on their i/o pins using the application program. both command and segment signals can be emulated in this way. lcd operation the lcd driving common pins, scom0~scom3, and segment pins, sseg0~ssegn, are pin shared with other i/o pins. these lcd driving pins are configured using a series of lcd control registers which in addition to controlling the overall on/off function also controls the bias voltage setup function. this enables the lcd com and seg driver to generate the necessary vss, (1 / 3)vdd, (2 / 3)vdd voltage and vdd levels for full lcd 1 / 3 bias operation. the slcden bit in the lcd control register is the overall master control for the lcd driver, and this bit is used in conjunction with the comnen and segnen bits to select which i/o port pins are used for lcd driving. note that the port control register does not need to first setup the pins as outputs to enable the lcd driver operation. rev. 1.00 142 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver ; 1 1 1 $ 1 $ 1 $ 1 $ ! 1 1 a 1 1 a 1 1 a ; 1 1 ; ; ? ! @ ; ? ! @ ; ; 1 1 - 7 1 < % " ; - 7 1 - ; lcd driver structure the accompanying waveform diagram shows a typical 1/3 bias lcd waveform generated using the application program. note that the depiction of a 1 in the diagram illustrates an illuminated lcd pixel. the com signal polarity generated on pins scom0~scom3, whether 0 or 1, are generated using the corresponding i/o data registers, which are bits pb0~pb3 in the pb register. a cyclic lcd waveform includes two frames, known as frame 0 and frame 1 for which the following offers a functional explanation. in frame 0 to select frame 0 clear the frame bit to 0. in frame 0, the com signal output can have a value of vdd, or have a vbias value of 1/3 vdd. the seg signal can have a value of vss, or have a vbias value of 2/3 vdd. in frame 1 in frame 1, the com signal output can have a value of vss, have a vbias value of 2/3 vdd. the seg signal can have a value of vdd have a vbias value of 1/3 vdd. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 143 february 1, 2011 $ $ $ $ ! 1 a 1 a 0 # 0 # 0 # ; ! ; ! ; ; 1 1 ; ! ; ! ; ; 1 1 ; ! ; ! ; ; 1 1 ; ! ; ! ; ; 1 1 ; ! ; ! ; ; 1 1 ; ! ; ! ; ; 1 1 note: the logical values shown in the diagram are the pb i/o register values, pb0~pb3. 1/3 bias lcd waveform the com0~comn waveform is controlled by the application program using the frame bit, and the corresponding i/o data register for the respective com pin to determine whether the com0~comn output has a value of either vdd, vss or vbias. the seg0~segm waveform is controlled in a similar way using the frame bit and the corresponding i/o data register for the respective seg pin to determine whether the seg0~segn output has a value of either vdd, vss or vbias. lcd bias control the lcd com and seg driver enable a range of selections to be provided to suit the requirement of the lcd panel which are being used. the bias resistor choice is implemented using the isel1 and isel0 bits in the lcd control register. lcd driver registers slcdc0 register b i t76543210 name frame isel1 isel0 slcden com3en com2en com1en com0en r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 frame : present frame output select -- frame 0 or frame 1 0: frame 0 1: frame 1 bit 6~5 isel1, isel0 : scom and sseg operating current selection -- v dd =5v 0: 25 a 1: 50 a 2: 100 a 3: 200 a bit 4 slcden : scom and sseg module on/off control 0: disable 1: enable the scomn and ssegm lines can be enabled using comnen and segmen if slcden=1. when slcden=0, then the scomn and ssegm outputs will be fixed at a vdd level. bit 3 com3en : scom3 or other function selection 0: other function 1: scom3 bit 2 com2en : scom2 or other function selection 0: other function 1: scom2 bit 1 com1en : scom1 or other function selection 0: other function 1: scom1 bit 0 com0en : scom0 or other function selection 0: other function 1: scom0 rev. 1.00 144 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver slcdc1 register b i t76543210 name seg7en seg6en seg5en seg4en seg3en seg2en seg1en seg0en r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 seg7en~seg0en : sseg7~sseg0 or other function selection 0: other function 1: sseg7~sseg0 slcdc2 register bs85b12-3 b i t76543210 name seg13en seg12en seg11en seg10en seg9en seg8en r/w r/w r/w r/w r/w r/w r/w por 000000 bit 7~6 unimplemented, read as 0 bit 5~0 seg13en~seg8en : sseg13~sseg8 or other function selection 0: other function 1: sseg13~sseg8 slcdc2 register BS85C20-3 b i t76543210 name seg15en seg14en seg13en seg12en seg11en seg10en seg9en seg8en r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~6 unimplemented, read as 0 bit 5~0 seg15en~seg8en : sseg15~sseg8 or other function selection 0: other function 1: sseg15~sseg8 slcdc3 register BS85C20-3 b i t76543210 name tck2ps seg21en seg20en seg19en seg18en seg17en seg16en r/w r/w r/w r/w r/w r/w r/w r/w por 0 000000 bit 7 tck2ps : tck2 pin remapping control described elsewhere bit 6 unimplemented, read as 0 bit 5~0 seg21en~seg16en : sseg21~sseg16 or other function selection 0: other function 1: sseg21~sseg16 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 145 february 1, 2011 led driver the devices contain an led driver function offering high current output drive capability which can be used to drive external leds. led driver operation depending upon which device is chosen various i/o pins have a capability of providing led high current drive outputs. device led drive pins bs85b12-3 pa0~pa7 (high source current) pb0~pb5 (high sink current) BS85C20-3 pa0~pa7 (high source current) pb0~pb7 (high sink current) pe0~pe5 (high source current) whether a normal current sink capability or high current sink capability is used, the selection is made using the sledcn registers. led driver registers sledc0 register bs85b12-3 b i t76543210 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 000000 bit 7~6 unimplemented, read as 0 bit 5~0 d5~d0 : pb5~pb0 i/o output sink current select 0: normal output sink current 1: 2 output sink current sledc0 register BS85C20-3 b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 d7~d0 : pb7~pb0 i/o output sink current select 0: normal output sink current 1: 2 output sink current rev. 1.00 146 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver sledc1 register all devices b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 d7~d0 : pa7~pa0 i/o output source current select 0: normal output source current 1: 2 output source current sledc2 register BS85C20-3 b i t76543210 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 000000 bit 7~6 unimplemented, read as 0 bit 5~0 d5~d0 : pe5~pe0 i/o output source current select 0: normal output source current 1: 2 output source current bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 147 february 1, 2011 application circuits note: # may be resistor or capacitor. the resistance of # must be greater than 1k or the capacitance of # must be less than 1nf. rev. 1.00 148 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver k k k ; ; 1 1 " ; 1 1 % ; 1 1 * ; 8 1 7 - 4 $ ( 7 # # 7 4 2 2 ; ; 1 1 g ; 2 + 2 1 - 5 1 5 1 $ . 1 1 a " - . " instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be implemented within 1 s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific immediate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. rev. 1.00 149 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is normally implemented by using registers. however, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 150 february 1, 2011 instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none rev. 1.00 151 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver mnemonic description cycles flag affected bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged. bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 152 february 1, 2011 instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc + [m] + c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and operation. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z rev. 1.00 153 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cy - cle instruction. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in con- junction with clr wdt2 and must be executed alternately with clr wdt2 to have ef- fect. repetitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in con - junction with clr wdt1 and must be executed alternately with clr wdt1 to have ef - fect. repetitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 154 february 1, 2011 cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain un - changed. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value resulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by adding 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the con - tents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf rev. 1.00 155 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 156 february 1, 2011 or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pend- ing when the reti instruction is executed, the pending interrupt routine will be processed before returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data mem - ory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none rev. 1.00 157 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 re - places the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 158 february 1, 2011 sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the spec- ified data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none rev. 1.00 159 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the spec - ified data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruc- tion. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the re- sult is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the re - sult is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is neg - ative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 160 february 1, 2011 swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain un - changed. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following in - struction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none rev. 1.00 161 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor operation. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 162 february 1, 2011 package information 24-pin skdip (300mil) outline dimensions ms-001d (see fig1) symbol dimensions in inch min. nom. max. a 1.230 1.280 b 0.240 0.280 c 0.115 0.195 d 0.115 0.150 e 0.014 0.022 f 0.045 0.070 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 31.24 32.51 b 6.10 7.11 c 2.92 4.95 d 2.92 3.81 e 0.36 0.56 f 1.14 1.78 g 2.54 h 7.62 8.26 i 10.92 rev. 1.00 163 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver fig1. full lead packages fig2. 1 / 2 lead packages ms-001d (see fig2) symbol dimensions in inch min. nom. max. a 1.160 1.195 b 0.240 0.280 c 0.115 0.195 d 0.115 0.150 e 0.014 0.022 f 0.045 0.070 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 29.46 30.35 b 6.10 7.11 c 2.92 4.95 d 2.92 3.81 e 0.36 0.56 f 1.14 1.78 g 2.54 h 7.62 8.26 i 10.92 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 164 february 1, 2011 mo-095a (see fig2) symbol dimensions in inch min. nom. max. a 1.145 1.185 b 0.275 0.295 c 0.120 0.150 d 0.110 0.150 e 0.014 0.022 f 0.045 0.060 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 29.08 30.10 b 6.99 7.49 c 3.05 3.81 d 2.79 3.81 e 0.36 0.56 f 1.14 1.52 g 2.54 h 7.62 8.26 i 10.92 rev. 1.00 165 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver 24-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 0.419 b 0.256 0.300 c 0.012 0.020 c 0.598 0.613 d 0.104 e 0.050 f 0.004 0.012 g 0.016 0.050 h 0.008 0.013 0 8 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.62 c 0.30 0.51 c 15.19 15.57 d 2.64 e 1.27 f 0.10 0.30 g 0.41 1.27 h 0.20 0.33 0 8 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 166 february 1, 2011 24-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.008 0.012 c 0.335 0.346 d 0.054 0.060 e 0.025 f 0.004 0.010 g 0.022 0.028 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.20 0.30 c 8.51 8.79 d 1.37 1.52 e 0.64 f 0.10 0.25 g 0.56 0.71 h 0.18 0.25 0 8 rev. 1.00 167 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver 28-pin skdip (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 1.375 1.395 b 0.278 0.298 c 0.125 0.135 d 0.125 0.145 e 0.016 0.020 f 0.050 0.070 g 0.100 h 0.295 0.315 i 0.375 symbol dimensions in mm min. nom. max. a 34.93 35.43 b 7.06 7.57 c 3.18 3.43 d 3.18 3.68 e 0.41 0.51 f 1.27 1.78 g 2.54 h 7.49 8.00 i 9.53 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 168 february 1, 2011 28-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 0.419 b 0.256 0.300 c 0.012 0.020 c 0.697 0.713 d 0.104 e 0.050 f 0.004 0.012 g 0.016 0.050 h 0.008 0.013 0 8 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.62 c 0.30 0.51 c 17.70 18.11 d 2.64 e 1.27 f 0.10 0.30 g 0.41 1.27 h 0.20 0.33 0 8 rev. 1.00 169 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver 28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.008 0.012 c 0.386 0.394 d 0.054 0.060 e 0.025 f 0.004 0.010 g 0.022 0.028 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.20 0.30 c 9.80 10.01 d 1.37 1.52 e 0.64 f 0.10 0.25 g 0.56 0.71 h 0.18 0.25 0 8 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 170 february 1, 2011 44-pin qfp (10mm 10mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.512 0.528 b 0.390 0.398 c 0.512 0.528 d 0.390 0.398 e 0.031 f 0.012 g 0.075 0.087 h 0.106 i 0.010 0.020 j 0.029 0.037 k 0.004 0.008 l 0.004 0 7 symbol dimensions in mm min. nom. max. a 13.00 13.40 b 9.90 10.10 c 13.00 13.40 d 9.90 10.10 e 0.80 f 0.30 g 1.90 2.20 h 2.70 i 0.25 0.50 j 0.73 0.93 k 0.10 0.20 l 0.10 0 7 rev. 1.00 171 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver reel dimensions sop 24w (300mil), sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.0 1.0 b reel inner diameter 100.0 1.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0 0.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.2 0.2 ssop 24s (150mil), ssop 28s (150mil) symbol description dimensions in mm a reel outer diameter 330.0 1.0 b reel inner diameter 100.0 1.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0 0.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.2 0.2 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 172 february 1, 2011 carrier tape dimensions sop 24w symbol description dimensions in mm w carrier tape width 24.0 0.3 p cavity pitch 12.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.9 0.1 b0 cavity width 15.9 0.1 k0 cavity depth 3.1 0.1 t carrier tape thickness 0.35 0.05 c cover tape width 21.3 0.1 rev. 1.00 173 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver ! " " # $ % & $ ' & ( % & ' # ' " $ ( ) ( ! # * + & ' & ssop 24s (150mil) symbol description dimensions in mm w carrier tape width 16.0 +0.3/-0.1 p cavity pitch 8.0 0.1 e perforation position 1.75 0.10 f cavity to perforation (width direction) 7.5 0.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 6.5 0.1 b0 cavity width 9.5 0.1 k0 cavity depth 2.1 0.1 t carrier tape thickness 0.30 0.05 c cover tape width 13.3 0.1 sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.0 0.3 p cavity pitch 12.0 0.1 e perforation position 1.75 0.10 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.85 0.10 b0 cavity width 18.34 0.10 k0 cavity depth 2.97 0.10 t carrier tape thickness 0.35 0.01 c cover tape width 21.3 0.1 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 174 february 1, 2011 ssop 28s (150mil) symbol description dimensions in mm w carrier tape width 16.0 0.3 p cavity pitch 8.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 7.5 0.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 6.5 0.1 b0 cavity width 10.3 0.1 k0 cavity depth 2.1 0.1 t carrier tape thickness 0.30 0.05 c cover tape width 13.3 0.1 rev. 1.00 175 february 1, 2011 bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver bs85b12-3/BS85C20-3 touch key flash mcu with lcd/led driver rev. 1.00 176 february 1, 2011 copyright 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com |
Price & Availability of BS85C20-3
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